Enabling High Performance Posit Arithmetic Applications Using Hardware Acceleration

112 Pages·2017·10.41 MB·English

Delft University of Technology
FacultyofElectricalEngineering,Mathematics,andComputerScience
DepartmentofQuantum&ComputerEngineering
Enabling High Performance Posit Arithmetic
Applications Using Hardware Acceleration
Thesisby:
LaurensvanDam
Advisors:
Prof. dr. H.P.Hofstee
Dr. ir. Z.Al-Ars
Committee:
Prof. dr. H.P.Hofstee(Chair)
Dr. ir. Z.Al-Ars
Dr. ir. M.Mo¨ller

Enabling High Performance Posit Arithmetic
Applications Using Hardware Acceleration
Thesis
submittedinpartialfulfillmentoftherequirementsforthedegreesof
MasterofScience
in
ComputerEngineering
&
EmbeddedSystems
by
LaurensvanDam
borninSpijkenisse,TheNetherlands
tobedefendedpubliclyonSeptember17,2018at15:00.
Studentnumber: 4203321
Submissiondate: September10,2018
Responsibleprofessors: prof.dr.H.P.Hofstee IBMResearch,TUDelft
dr.ir.Z.Al-Ars TUDelft
Thesiscommittee: prof.dr.H.P.Hofstee IBMResearch,TUDelft,jurychairman
dr.ir.Z.Al-Ars TUDelft,jurymember
dr.ir.M.Mo¨ller TUDelft,jurymember
CE-MS-2018-07
ISBN978-94-6186-957-9
Quantum&ComputerEngineering
FacultyofElectricalEngineering,Mathematics,andComputerScience
DelftUniversityofTechnology
Mekelweg4
2628CDDelft
TheNetherlands

Abstract
Thedemandforhigherprecisionarithmeticisincreasingduetotherapiddevelopmentof
newcomputingparadigms. Thenovelpositnumberrepresentationsystem,asintroduced
byJohnL.Gustafson, claimstobeabletoprovidemoreaccurateanswerstomathemati-
calproblemswithequalorlessnumberofbitscomparedtothewell-establishedIEEE754
floatingpointstandard.
Inthiswork,theperformanceofthepositnumberformatintermsofdecimalaccuracyis
analyzedandcomparedtoalternativenumberrepresentations.
A framework for performing high-precision posit arithmetic in reconfigurable logic is
presented. Thesupportedarithmeticoperationscanbeperformedwithoutroundingoff
intermediateresults,minimizingthelossofdecimalaccuracy. Theproposedpositarith-
meticunitsachieveapproximately250MPOPSforaddition,160MPOPSformultiplication
and180MPOPSforaccumulationoperations.
A hardware accelerator for performing Level 1 BLAS operations on (sparse) posit col-
umn vectors is presented. For the calculation of the vector dot product for an input vec-
tor length of 106 elements, a speedup of approximately 15000× compared to software
is achieved. The decimal accuracy is improved by one decimal of accuracy on average
compared to posit emulation in software, and two additional decimals of accuracy are
achievedcomparedtocalculationusingtheIEEE754floatingpointformat.
Astudyoftheapplicationofpositarithmeticinthefieldofbioinformaticsisperformed.
The effect on decimal accuracy of the pair-HMM forward algorithm by replacing tradi-
tional floating point arithmetic with posit arithmetic is analyzed. It is shown that the
maximumachievabledecimalaccuracyusingpositarithmeticishighercomparedtothe
IEEEfloatingpointformatforthesamenumberofrequiredbits.
The design of a hardware accelerator for the pair-HMM forward algorithm using posit
arithmeticisproposedfortwodifferentinterfaces: astreaming-basedacceleratorandan
accelerator interfacing with Apache Arrow columnar data, both connected by the CAPI
(SNAP)platform. Overall,thepositnumberformatbeatstheIEEEfloatingpointnumber
formatintermsofdecimalaccuracy,rangingfromanimprovementof0.5to1additional
decimal of accuracy for the performed test cases. A throughput of 1.6 and 1 giga cell
updatespersecondismeasuredforbothacceleratorimplementations,respectively.
3

Preface
Beforeyouliesthefinalproductofmyworkofthelastninemonths,titled”EnablingHigh
PerformancePositArithmeticApplicationsUsingHardwareAcceleration”.
I could not have accomplished this work without the strong support from people I care
about. First, my parents, who have always supported me with love and understanding.
Secondly,myfriends,whoweretheretosupportmeduringmyendeavors(andtodistract
meonceinawhile).
MyspecialthanksgoestoJinhoLeeforthehelpwithtestinganddebuggingmyhardware
designs.
ThankyouMatthiasMo¨llerforagreeingtobepartofthegraduationcommitteeandpro-
vidingmewithusefulresearchdirections.
Lastly, I would like to thank my thesis supervisors, Peter Hofstee and Zaid Al-Ars, each
ofwhomhasprovidedpatientguidancethroughoutthisresearchprocess.
Thankyouallforyourunwaveringsupport.
LaurensvanDam
Delft,TheNetherlands
September10,2018
5

Contents
ListofFigures 11
ListofTables 13
1 Introduction 17
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2 ThesisAim&Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.3 ThesisOutline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2 Background 21
2.1 TheUnumArithmeticFramework . . . . . . . . . . . . . . . . . . . . . . . 21
2.1.1 TypeIUnum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.1.2 TypeIIUnum&SORNs . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.1.3 TypeIIIUnum(Posit) . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2 FeatureComparisonofIEEEFloatandPosit . . . . . . . . . . . . . . . . . . 28
2.2.1 Not-A-Number(NaN) . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2.2 NegativeZeroand±∞ . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2.3 Critique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3 PositArithmeticHardwareImplementations . . . . . . . . . . . . . . . . . 30
2.4 AlternativeHigh-PrecisionNumberFormats . . . . . . . . . . . . . . . . . 31
2.4.1 DecimalFloatingPoint . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.4.2 BoostMultiprecision . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.5 CompilerOptimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.5.1 OptimizationLevel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.5.2 SubnormalNumbers . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.5.3 Multiply-Accumulate . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.6 MeasureofDecimalAccuracy . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.7 ApacheArrow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3 ApplicationsinBioinformatics 37
3.1 PairHiddenMarkovModel(Pair-HMM) . . . . . . . . . . . . . . . . . . . . 37
3.1.1 Pair-HMMForwardAlgorithm . . . . . . . . . . . . . . . . . . . . . 39
3.1.2 Pair-HMMHardwareAcceleration . . . . . . . . . . . . . . . . . . . 41
7
8 CONTENTS
3.2 GATK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.3 Pair-HMMinFloatandPositRepresentation . . . . . . . . . . . . . . . . . 44
3.3.1 QuantitativeAnalysis . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.2 PhredScale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3.3 Pair-HMMForwardAlgorithm . . . . . . . . . . . . . . . . . . . . . 49
4 FrameworkforHardwarePositArithmetic 53
4.1 FrameworkDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.1.1 PositExtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.1.2 PositNormalization . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.1.3 PositAdder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.1.4 PositMultiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.1.5 PositAccumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2 HardwareImplementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.3 EvaluationofFrameworkAccuracy&Performance . . . . . . . . . . . . . . 59
4.3.1 DecimalAccuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.3.2 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5 PositVectorArithmeticAccelerator 65
5.1 AcceleratorDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.2 HardwareImplementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3 EvaluationofPerformance&Accuracy . . . . . . . . . . . . . . . . . . . . . 68
5.3.1 VectorOperations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.3.2 Gram-SchmidtProcess . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6 Pair-HMMPositAccelerator 77
6.1 OverallDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.1.1 ProcessingElement(PE) . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1.2 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.2 StreamingImplementation(CAPI) . . . . . . . . . . . . . . . . . . . . . . . 81
6.2.1 AcceleratorDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.2.2 HardwareImplementation . . . . . . . . . . . . . . . . . . . . . . . 83
6.2.3 EvaluationofPerformance&Accuracy . . . . . . . . . . . . . . . . 84
6.3 Higher-AccuracyIn-MemoryHardwareImplementation . . . . . . . . . . 87
6.3.1 AcceleratorDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.2 HardwareImplementation . . . . . . . . . . . . . . . . . . . . . . . 91
6.3.3 EvaluationofPerformance&Accuracy . . . . . . . . . . . . . . . . 91
6.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7 Conclusions 97
A Pair-HMMPseudocode 101