Embedded memories for nano-scale VLSIs

387 Pages·2009·24.135 MB·English

by  Kevin Zhang (auth.), Kevin Zhang (eds.)

Kevin Zhang
Editor
Embedded Memories
for Nano-Scale VLSIs
123
Editor
KevinZhang
IntelCorporation
2501NW.229thAve.
Hillsboro,OR97124
USA
[email protected]
ISBN978-0-387-88496-7 e-ISBN978-0-387-88497-4
DOI10.1007/978-0-387-88497-4
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(cid:2)c SpringerScience+BusinessMedia,LLC2009
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Contents
1 Introduction.................................................... 1
KevinZhang
2 Embedded Memory Architecture for Low-Power Application
Processor....................................................... 7
HoiJunYooandDonghyunKim
3 EmbeddedSRAMDesigninNanometer-ScaleTechnologies.......... 39
HiroyukiYamauchi
4 UltraLowVoltageSRAMDesign ................................. 89
NaveenVermaandAnanthaP.Chandrakasan
5 EmbeddedDRAMinNano-scaleTechnologies......................127
JohnBarth
6 EmbeddedFlashMemory........................................177
HidetoHidaka
7 EmbeddedMagneticRAM .......................................241
HidetoHidaka
8 FeRAM ........................................................279
ShoichiroKawashimaandJeffreyS.Cross
9 StatisticalBlockade:EstimatingRareEventStatisticsforMemories ..329
AmithSingheeandRobA.Rutenbar
Index .............................................................383
v
Contributors
JohnBarth IBM,EssexJunction,Vermont,[email protected]
AnanthaP.Chandrakasan MassachusettsInstituteofTechnologyCambridge,
MA,USA
JeffreyS.Cross TokyoInstituteofTechnology,2-12-1Ookayama,Meguro-ku,
Tokyo152-8550,Japan,[email protected]
HidetoHidaka MCUTechnologyDivision,RenesasTechnologyCorporation,
4-1Mizuhara,Itami,664-0005,Japan,[email protected]
Shoichiro Kawashima Fujitsu Microelectronics Limited, System Micro
Division,1-1Kamikodanaka4-chome,Nakahara-ku,Kawasaki,211-8588,Japan
[email protected]
DonghyunKim KAIST
Rob A. Rutenbar Electrical and Computer Engineering, Carnegie Mellon
University,Pittsburgh,PA,USA,[email protected]
AmithSinghee IBM,ThomasJ.WatsonResearchCenter,YorktownHeights,NY,
USA
NaveenVerma MassachusettsInstituteofTechnology,Cambridge,MA,USA,
[email protected]
HiroyukiYamauchi FukuokaInstituteofTechnology,Fukuoka,Japan
HoiJunYoo KAIST
KevinZhang IntelCorporation,Hillsboro,OR,USA
vii
Chapter 1
Introduction
KevinZhang
Advancement of semiconductor technology has driven the rapid growth of very
large scale integrated (VLSI) systems for increasingly broad applications, includ-
ing high-end and mobile computing, consumer electronics such as 3D gaming,
multi-function or smart phone, and various set-top players and ubiquitous sensor
and medical devices. To meet the increasing demand for higher performance and
lowerpowerconsumptioninmanydifferentsystemapplications,itisoftenrequired
tohavealargeamountofon-dieorembeddedmemorytosupporttheneedofdata
bandwidthinasystem.Thevarietiesofembeddedmemoryinagivensystemhave
alsobecomeincreasinglymorecomplex,rangingfromstatictodynamicandvolatile
tononvolatile.
Among embedded memories, six-transistor (6T)-based static random access
memory (SRAM) continues to play a pivotal role in nearly all VLSI systems due
toitssuperiorspeedandfullcompatibilitywithlogicprocesstechnology.Butasthe
technologyscalingcontinues,SRAMdesignisfacingseverechallengeinmaintain-
ing sufficient cell stability margin under relentless area scaling. Meanwhile, rapid
expansioninmobileapplication,includingnewemergingapplicationinsensorand
medical devices, requires far more aggressive voltage scaling to meet very strin-
gentpowerconstraint.Manyinnovativecircuittopologiesandtechniqueshavebeen
extensivelyexploredinrecentyearstoaddressthesechallenges.
Dynamic random access memory (DRAM) has long been an important semi-
conductormemoryforitswell-balancedperformanceanddensity.Withincreasing
demand for on-die dense memory, one-transistor and one-capacitor (1T1C)-based
DRAM has found varieties of embedded applications in providing the memory
bandwidth for system-on-chip (SOC) applications. With increasing amount of on-
die cache memory for high-end computing and graphics application, embedded
DRAM (eDRAM) is becoming a viable alternative to SRAM for large on-die
memory. To meet product requirements for eDRAM while addressing continuous
technologyscaling,manynewmemorycircuitdesigntechnologies,whichareoften
K.Zhang( )
B
IntelCorporation, 2501NE229thAve,Hillsboro,OR97124,USA
e-mail:[email protected]
K.Zhang(ed.),EmbeddedMemoriesforNano-ScaleVLSIs,SeriesonIntegrated 1
CircuitsandSystems,DOI10.1007/978-0-387-88497-4 1,
(cid:2)C SpringerScience+BusinessMedia,LLC2009
2 K.Zhang
drasticallydifferentfromcommodityDRAMdesign,havetobedevelopedtosub-
stantiallyimprove the eDRAMperformance whilekeeping theoverall power con-
sumptionatminimum.
Solid-statenonvolatilememory(NVM)hasplayedanincreasinglyimportantrole
inbothcomputingandconsumerelectronics.Manynewapplicationsinmostrecent
consumerelectronicsandautomobileshavefurtherbroadenedtheembeddedappli-
cationforNVM.AmongvariousNVMtechnologies,floating-gate-basedNORflash
has been the early technology choice for embedded logic applications. With tech-
nologyscalingchallengesinthefloating-gatetechnologies,includingtheincreasing
needforintegratingNVMalongwithmoreadvancedlogictransistors,varietiesof
NVM technologies have been extensively explored, including alternative technol-
ogy based on charge-trapping mechanism (Fig. 1.1). More efficient circuit design
techniquesforembeddedflashalsohavetobeexploredtoachieveoptimalproduct
goals.
With increasing demand of NVM for further scaling of the semiconductor
technology, several emerging memory technologies have drawn increasingly more
attention, including magnetic RAM (MRAM), phase-change RAM (PRAM), and
ferroelectric RAM (FeRAM). These new technologies not only address some of
the fundamental scaling limits in the traditional solid-state memories, but also
have brought new electrical characteristics in the nonvolatile memories on top of
the random accessing capability. For example, MRAM can offer significant speed
improvement over traditional floating-gate memory, which could open up whole
new applications. FeRAM can operate at lower voltage and consume ultra low
power,whichhasalreadymadeitinto“smart-card”marketplacetoday.Thesenew
memorytechnologiesalsorequireanewsetofcircuittopologiesandsensingtech-
niquestomaximizethetechnologybenefits,incomparisontothetraditionalNVM
design.
With rapid downward scaling of the feature size of memory device by tech-
nology and drastic upward scaling of number of storage elements per unit area,
process-induced variation in memory has become increasingly important for both
memory technology and circuit design. Statistical design methodology has now
75
65
NMOS σVTN
55
(one device)
V) 45 Minimum device
m
(
VT35
σ
25 Nominal device
15
Fig.1.1 Transistorvariation
trendwithtechnology 5
scaling[1] 113300nnmm 9900nnmm 6655nnmm 4455nnmm
1 Introduction 3
Fig.1.2 Relative
performanceamongdifferent
typesofembeddedmemories
become essential in developing reliable memory for high-volume manufacturing.
Therequiredstatisticalmodelingandoptimizationcapabilityhasgrownfarbeyond
thememorycelltocomprehendmanysensitiveperipheralcircuitsintheentiremem-
ory block, such as critical signal development paths. Advanced statistical design
techniquesareclearlyrequiredintoday’smemorydesign.
In traditional memory field, there is often a clear technical boundary between
different kinds of memory technology, e.g., SRAM and DRAM, volatile and non-
volatile.Withgrowingdemandforon-diememorytomeettheneedoffutureVLSI
systemdesign,itisveryimportanttotakeabroaderviewofoverallmemoryoptions
in order to make the best design tradeoff in achieving optimal system-level power
andperformance.Figure1.2illustratesthepotentialtradeoffamongthesedifferent
memories.Withthisinmind,thisbookintendstoprovideastate-of-the-artviewon
mostrecentadvancementsofmemorytechnologiesacrossdifferenttechnicaldisci-
plines.Bycombiningthesedifferentmemoriestogetherinoneplace,itshouldhelp
readerstogainamuchbroadenedviewonembeddedmemorytechnologyforfuture
applications. Each chapter of the book is written by a set of leading experts from
bothindustryandacademiatocoverawidespectrumofkeymemorytechnologies
alongwithmostsignificanttechnicaltopicsineacharea,rangingfromkeytechnical
challengestotechnologyanddesignsolutions.Thebookisorganizedasfollows:
1.1 Chapter2:EmbeddedMemoryArchitectureforLow-Power
ApplicationProcessor,byHoiJunYoo
In this chapter, an overview on embedded memory architecture for varieties of
mobile applications is provided. Several real product examples from advanced
application processors are analyzed with focus on how to optimize the memory
4 K.Zhang
architecturetoachievelow-powerandhigh-performancegoal.Thechapterintends
toprovidereadersanarchitecturalviewontheroleofembeddedmemoryinmobile
applications.
1.2 Chapter3:EmbeddedSRAMDesigninNanometer-Scale
Technologies,byHiroyukiYamauchi
Thischapterdiscusseskeydesignchallengesfacingtoday’sSRAMdesigninnano-
scale CMOS technologies. It provides a broad coverage on latest technology and
design solutions to address SRAM scaling challenges in meeting power, density,
andperformancegoalforproductapplications.Atradeoffforeachtechnologyand
designsolutionisthoroughlydiscussed.
1.3 Chapter4:UltraLowVoltageSRAMDesign,byNaveen
VermaandAnanthaP.Chandrakasan
In this chapter, an emerging family of SRAM design is introduced for ultra-low-
voltage operation in highly energy-constrained applications such as sensor and
medicaldevices.Manystate-of-the-artcircuittechnologiesarediscussedforachiev-
ing very aggressive voltage-scaling target. Several advanced design implementa-
tionsforreliablesub-thresholdoperationareprovided.
1.4 Chapter5:EmbeddedDRAMinNano-ScaleTechnologies,
byJohnBarth
Thischapterdescribesthestate-of-the-arteDRAMdesigntechnologiesforvarieties
of applications, including both consumer electronics and high-performance com-
puting in microprocessors. Array architecture and circuit techniques are explored
to achieve a balanced and robust design based on high-performance logic process
technologies.
1.5 Chapter6:EmbeddedFlashMemory,byHidetoHidaka
This chapter provides a very comprehensive view on the state of embedded flash
memory technology in today’s industry, including process technology, product
application,andfuturetrend.Severalkeytechnologyoptionsandtheirtradeoffsare
discussed. Product design examples for micro-controller unit (MCU) are analyzed
downtocircuitimplementationlevel.
1 Introduction 5
1.6 Chapter7:EmbeddedMagneticRAM,byHidetoHidaka
Magnetic RAM has become a key candidate for new applications in nonvolatile
applications. This chapter introduces both key technology and circuit design ele-
mentsassociatedwiththisnewtechnology.Thefutureapplicationandmarkettrend
forMRAMarealsodiscussed.
1.7 Chapter8:FeRAM,byShoichiroKawashima
andJeffreyS.Cross
Thischapterintroducesthelatestmaterial,device,andcircuitadvancementinfer-
roelectricRAM(FeRAM).Withexcellentwrite-time,randomaccessingcapability,
andcompatibilitywithlogicprocess,FeRAMhaspenetratedintoseveralapplication
areas.Realproductexamplesareprovidedalongwithfuturetrendofthetechnology.
1.8 Chapter9:StatisticalBlockade:EstimatingRareEvent
StatisticsforMemories,byAmithSinghee
andRobA.Rutenbar
This chapter introduces a comprehensive statistical design methodology that is
essential in today’s memory design. The core of this methodology is called sta-
tistical blockade and it combines Monte Carlo simulation, machine learning, and
extreme value theory in effectively predicting rare failure (> 5 sigma) event. Real
design examples are used to illustrate the benefit of the methodology in memory
designandoptimization.
Reference
1. K.Kuhn,“ReducingVariationinAdvancedLogicTechnologies:ApproachestoProcessand
DesignforManufacturabilityofNanoscaleCMOS,”IEEEIEDMTechDigest,pp.471–474,
Dec.2007.
Chapter 2
Embedded Memory Architecture for Low-Power
Application Processor
HoiJunYooandDonghyunKim
2.1 MemoryHierarchy
2.1.1 Introduction
Currently, the state-of-the-art high-end processors operate at 3–4 GHz frequency
whereas even the fastest off-chip memory operates at justaround 600 MHz [1–6].
In decades, along with advances in processor technology, the speed gap between
processorsandmemorieshasbecomeintolerablylarge[7],andthisspeedgaphas
driventheprocessordesignerstointroduceamemoryhierarchyintotheprocessor
architecture. For processors, it is ideal to have indefinitely large memory with no
accesslatencies[8].However,implementinglarge-capacitymemorywithfastoper-
ation speed is infeasible due to the physical limitations of the electrical circuits.
Thus,thecapacityisusuallytradedoffwiththeoperationspeedinmemorydesigns.
For example, on-chip L1 caches are able to operate as fast as the state-of-the-art
processorcoresbuthaveatmostfewkilobytescapacity.Ontheotherhand,off-chip
DRAMsarecapableofstoringfewgigabytesthoughtheiroperationfrequenciesare
justaroundhundredsofmegahertz.
The memory hierarchy is an arrangement of different types of memories with
different capacities and operation speeds to approximate the ideal memory behav-
ior in a cost-efficient way. The idea of memory hierarchy comes from observing
twocommoncharacteristicsofthememoryaccessesinthewiderangeofprograms,
namely temporal locality and spatial locality. When a program accesses a certain
data address repeatedly for a while, it is temporal locality. Spatial locality means
thatthememoryaccessesoccurwithinasmallregionofmemoryforashortdura-
tion.Duetotheselocalities,embeddingasmallbutfastmemoryissufficienttopro-
videaprocessorwithfrequentlyrequireddataforashortperiodoftime.However,
H.J.Yoo( )
B
KAIST
K.Zhang(ed.),EmbeddedMemoriesforNano-ScaleVLSIs,SeriesonIntegrated 7
CircuitsandSystems,DOI10.1007/978-0-387-88497-4 2,
(cid:2)C SpringerScience+BusinessMedia,LLC2009