Electronic device architectures for the nano-CMOS era: from ultimate CMOS scaling to beyond CMOS devices

440 Pages·2008·24.43 MB·English

by  Simon Deleonibus

Electronic Device Architectures
for the
Nano-CMOS Era
From Ultimate CMOS Scaling
to Beyond CMOS Devices
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TThhiiss ppaaggee iinntteennttiioonnaallllyy lleefftt bbllaannkk
Electronic Device Architectures
for the
Nano-CMOS Era
From Ultimate CMOS Scaling
to Beyond CMOS Devices
Editor
Simon Deleonibus
CEA-LETI, France
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Published by
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British Library Cataloguing-in-Publication Data
A catalogue record for this book is available from the British Library.
ELECTRONIC DEVICE ARCHITECTURES FOR THE NANO-CMOS ERA
From Ultimate CMOS Scaling to Beyond CMOS Devices
Copyright © 2009 by Pan Stanford Publishing Pte. Ltd.
All rights reserved. This book, or parts thereof, may not be reproduced in any form or by any means,
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ISBN-13978-981-4241-28-1
ISBN-10981-4241-28-8
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Rhaimie - Electronic device Archi.pmd 1 12/29/2008, 2:21 PM
RPS ElectronicDeviceArchitecturesfortheNano-CMOSEra “Preface” 2008/7/28 v
Acknowledgments
Iwishtocongratulateallcontributorsandtheirpeers,allofwhomareworld-
renownedresearchersfromtopuniversities,institutionsandorganisations,
for the results of their research. Their convictions and efforts were key
elementsforthesuccessofthisenterprise.
I wish to specially acknowledge Professor Hiroshi Iwai of Tokyo
Institute of Technology (Yokohama, Japan) and former IEEE Electron
DeviceSocietyPresident,forhisadvice,chaptercontributionandpersonal
encouragement.
The support of Professors Jean-Pierre Colinge (Tyndall, Cork, Ire-
land), Cor Claeys (IMEC, Leuven, Belgium), the present IEEE Electron
Device Society President, Masataka Hirose (AIST, Tsukuba, Japan), and
Jim Hutchby (SRC, Durham-NC, USA), to the promotion of the book is
alsoappreciated.TheirinfluenceinthefieldofNanoelectronics,Nanotech-
nology and Nanoscience is a reflection of the high scientific level of the
differentcontributions.
I have special thanks to address to Mr. Stanford Chong, Mr. Rhaimie
WahapandstaffmembersofPanStanfordPublishingfortheirresponsive-
nessandimmensepatiencedemonstratedthroughoutthewholeprocessof
thebook’spublishing.
Finally, none of this would have been possible without the support of
CEA-LETI.Themoralsupportandattentionfrommywife,Genevièveand
mysonTristan,havebeenofutmostimportancetome.Iwishtodedicate
thisworktothem.
SimonDeleonibus
CEA-LETI/MINATEC
CEA-Grenoble,17ruedesMartyrs38054
GrenobleCedex09,France
[email protected]
v
RPS ElectronicDeviceArchitecturesfortheNano-CMOSEra “Preface” 2008/7/28 vi
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RPS ElectronicDeviceArchitecturesfortheNano-CMOSEra “content” 2008/7/28 vii
Contents
Acknowledgments v
Introduction ix
Section1 CMOSNanoelectronics.ReachingtheEndof 1
theRoadmap
Sub-section1.1 CoreCMOS 3
Chapter1 PhysicalandTechnologicalLimitationsof 5
NANOCMOSDevicestotheEndofthe
RoadmapandBeyond
SimonDeleonibus,OlivierFaynot,
BarbaradeSalvo,ThomasErnst,
CyrilleLeRoyer,ThierryPoirouxand
MaudVinet
Chapter2 AdvancedCMOSDevicesonBulkandSOI: 55
Physics,ModelingandCharacterization
ThierryPoirouxandGillesLeCarval
Chapter3 DevicesStructuresandCarrierTransport 81
PropertiesofAdvancedCMOSusingHigh
MobilityChannels
ShinichiTakagi,TsutomuTezuka,
ToshifumiIrisawa,ShuNakaharai,
ToshinoriNumata,KojiUsuda,
NaoharuSugiyama,MasatoShichijo,
RyoshoNakaneandSatoshiSugahara
Chapter4 High-KGateDielectrics 105
HeiWong,KenjiShiraishi,KuniyukiKakushima,
andHiroshiIwai
Chapter5 FabricationofSourceandDrain—Ultra 141
ShallowJunction
BunjiMizuno
vii
RPS ElectronicDeviceArchitecturesfortheNano-CMOSEra “content” 2008/7/28 viii
ElectronicDeviceArchitecturesfortheNano-CMOSEra
Chapter6 NewInterconnectSchemes:EndofCopper, 159
OpticalInterconnects?
SuzanneLaval,LaurentVivien,EricCassan,
DelphineMarris-MoriniandJean-MarcFédéli
Sub-section1.2 MemoryDevices 185
Chapter7 TechnologiesandKeyDesignIssuesfor 187
MemoryDevices
KinamKimandGitaeJeong
Chapter8 FeRAMandMRAMTechnologies 211
YoshihiroArimoto
Chapter9 AdvancedChargeStorageMemories:From 241
SiliconNanocrystalstoMolecularDevices
BarbaraDeSalvoandGabrielMolas
Section2 CMOSNanoelectronics.Reachingthe 277
EndoftheRoadmap
Chapter10 SingleElectronDevicesandApplications 279
JacquesGautier,XavierJehl,andMarcSanquer
Chapter11 ElectronicPropertiesofOrganicMonolayers 299
andMolecularDevices
DominiqueVuillaume
Chapter12 CarbonNanotubeElectronics 333
VincentDerycke,AriannaFiloramoand
Jean-PhilippeBourgoin
Chapter13 SpinElectronics 365
Kyung-JinLeeandSangHoLim
Chapter14 TheLongerTerm:QuantumInformation 387
ProcessingandCommunication
PhilippeJorrand
Index 421
viii S.Deleonibus
RPS ElectronicDeviceArchitecturesfortheNano-CMOSEra “intro” 2008/7/28 ix
Introduction
Electronic Devices Architectures for the
NANO-CMOS Era — From Ultimate CMOS
Scaling to Beyond CMOS devices
Since the invention of the first calculation machines, miniaturization has
been a constant challenge to increase speed and complexity. Electronic
deviceshavebrought,andwillbringinthefuture,afarincreasingnumber
of new functions to the basic computing systems such as fast data com-
puting, telecommunication, several kinds of actuations,…which are col-
lectivelyfabricatedonthesamephysicalobjectnamedsolidstatecircuit1,
integratedcircuitor“chip”.Electronicdevicesaresosmall,thatbillionsof
basic functions are accessible in a hand held system. Moreover, their unit
cost has been divided by more than a factor of 100 millions over the past
30years!Thecollectivefabricationofelectronicdevicescoupledwiththe
increase of their speed has given a tremendous success, which is unique
in the history of mankind, to Micro and Nanoelectronics by continuously
introducing innovations in the fabrication process (Fig. 1). Linear scaling
ofdevicesdimensionstoaquasi-nanometerlevelallowstobuildcomplex
systemsintegratedonachip(Fig.1)whichreducedrasticallytheirvolume
andpowerconsumptionperfunction,whilsttremendouslyincreasingtheir
speed.Inthefuture,opportunitieswillappeartobuildsytemsinamolecule.
Nanoscience and Nanotechnology researchers join their efforts to Nano-
electronics actors in order to offer mankind possibilities of pervasion of
theirknowledgeintotheconstructionofnanosystems.
Electronic Devices Architectures for the NANO-CMOS Era, is a
review for the use of Nanoelectronics, Nanoscience and Nanotechnology
researchersandengineers,inwhichweaddress:
(1) theoptionstolinearlyscaledownlogicCMOSormemories;
(2) thepossiblecompetingbreakthrougharchitecturesallowingtorelaxon
thelinearscalingchallenges;
(3) thenewpathsforintegratedelectronics.
Thependingalternativesaretwoways:
(1) try to continue the scaling of Ultimate CMOS requesting new materi-
alsor
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