Table Of ContentGracieli Posser · Sachin S. Sapatnekar
Ricardo Reis
Electromigration
Inside Logic Cells
Modeling, Analyzing and Mitigating
Signal Electromigration in NanoCMOS
Electromigration Inside Logic Cells
Gracieli Posser • Sachin S. Sapatnekar
Ricardo Reis
Electromigration Inside
Logic Cells
Modeling, Analyzing and Mitigating Signal
Electromigration in NanoCMOS
123
GracieliPosser SachinS.Sapatnekar
InstitutodeInformática-PPGC/PGMicro DepartmentofElectricalandComputer
UniversidadeFederaldoRioGrandedoSul Engineering
(UFRGS) UniversityofMinnesota
PortoAlegre,RioGrandedoSul,Brazil Minneapolis,MN,USA
RicardoReis
InstitutodeInformática-PPGC/PGMicro
UniversidadeFederaldoRioGrandedoSul
(UFRGS)
PortoAlegre,RioGrandedoSul,Brazil
ISBN978-3-319-48898-1 ISBN978-3-319-48899-8 (eBook)
DOI10.1007/978-3-319-48899-8
LibraryofCongressControlNumber:2016959979
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Preface
Electromigration(EM)inon-chipmetalinterconnectsisacriticalreliability-driven
failuremechanisminnanometer-scaletechnologies.Usually,worksintheliterature
thataddressEMareconcernedwithpowernetworkEMandcelltocellinterconnec-
tionEM.ThisworkdealswithanotheraspectoftheEMproblem,thecell-internal
EM. This work specifically addresses the problem of electromigration on signal
interconnectsandonVddandVssrailswithinastandardcell.Therearefewstudies
intheliteratureaddressingthisproblem,andtheonesthatcanmodelEMareusing
a very simple model. To our best knowledge, this is the first work that analyzes,
models, and reduces the EM effects on the signals inside cells by projecting
the pin placement. In this work, cell-internal EM is modeled incorporating Joule
heating effects and currentdivergenceand is used to analyze the lifetime of large
benchmark circuits. An efficient graph-based algorithm is developed to speed up
thecharacterizationofcell-internalEM.Thisalgorithmestimatesthecurrentswhen
the pin position is moved avoiding a new characterization for each pin position,
producinganaverageerrorofjust0.53%comparedtoSPICEsimulation.Amethod
foroptimizingtheoutput,Vdd,andVsspinplacementofthecellsandconsequently
to optimize the circuit lifetime using minor layout modifications is proposed. To
optimizethe TTFof the circuits, just the LEF file is changedavoidingthe critical
pinpositions;thecelllayoutisnotchanged.Thecircuitlifetimecouldbeimproved
upto62.50%atthesamearea,delay,andpowerbecausechangingthepinpositions
affects very marginally the routing. This lifetime improvement is achieved just
avoidingthecriticaloutputpinpositionsofthecells,78.54%avoidingthecritical
Vdd pin positions, 89.89% avoiding the critical Vss pin positions, and up to
80.95% (from 1 to 5.25 years) when output, Vdd, and Vss pin positions are all
optimizedsimultaneously.We alsoshowthelargestandsmallestlifetimesoverall
pincandidatesforasetofcells,wherethelifetimeofacellcanbeimprovedupto
76(cid:2)bytheoutputpinplacement.Moreover,someexamplesarepresentedtoexplain
why some cells have a larger TTF improvement when the output pin position is
changed.Celllayoutoptimizationchangesaresuggestedtoimprovethelifetimeof
thecellsthathaveaverysmallTTFimprovementbypinplacement.Atcircuitlevel,
v
vi Preface
wepresentananalysisoftheEMeffectsondifferentmetallayersanddifferentwire
lengthsforsignalwires(nets)thatconnectcells.
PortoAlegre,RioGrandedoSul,Brazil GracieliPosser
Minneapolis,MN,USA SachinS.Sapatnekar
PortoAlegre,RioGrandedoSul,Brazil RicardoReis
Acknowledgments
ThisworkwaspartiallysupportedbytheBrazilianNationalCouncilforScientific
andTechnologicalDevelopment(CNPq,Brazil),CoordinationfortheImprovement
ofHigherEducationPersonnel(CAPES),andtheGraduateProgramsinComputer
Science (PPGC) and on Microelectronics (PGMICRO), Institute of Informatics,
UniversidadeFederaldoRioGrandedoSul(UFRGS)inBrazil.
We thanktheUniversityofMinnesotaandtwootherresearchers:VivekMishra
(fromtheUniversityofMinnesota)andPalkeshJain(fromQualcommIndia).
vii
Contents
1 Introduction .................................................................. 1
1.1 ReliabilityandElectromigration ....................................... 2
1.2 ElectromigrationinFutureTechnologies.............................. 3
1.3 MotivationandContributions .......................................... 5
1.4 MonographOutline ..................................................... 10
2 StateoftheArt............................................................... 11
2.1 MitigatingtheEMEffectsinDifferentICDesignFlowStages...... 11
2.1.1 ManagingElectromigrationinLogicDesigns................. 13
2.1.2 ElectromigrationImpactinFutureTechnologies ............. 15
2.1.3 SmartNon-defaultRoutingforClockPowerReduction...... 16
2.1.4 ImpactsofElectromigrationAwareness....................... 17
2.2 MitigatingtheEMEffectsinDifferentTypesofInterconnections... 20
2.2.1 TSVs ............................................................ 20
2.2.2 PowerDeliveryNetwork....................................... 21
2.2.3 ClockNetwork.................................................. 23
2.2.4 Vias.............................................................. 24
2.2.5 SignalInterconnects............................................ 26
2.2.6 Cell-InternalEM................................................ 27
2.3 SummaryofRelatedWorks ............................................ 30
2.4 Conclusions ............................................................. 31
3 ModelingCell-InternalEM................................................. 33
3.1 ModelingTime-to-FailureUnderEM.................................. 33
3.2 JouleHeating............................................................ 35
3.2.1 LocalHotSpotsfromJouleHeating........................... 36
3.3 CurrentDivergence ..................................................... 37
3.3.1 New ElectromigrationValidation:Via Node
VectorMethod .................................................. 37
3.3.2 ApplyingCurrentDivergenceintheProposedEMModel... 40
3.3.3 TheImpactofBlechLengthonCell-InternalInterconnects.. 42
3.4 Conclusions ............................................................. 42
ix
x Contents
4 CurrentCalculation ......................................................... 45
4.1 CurrentFlowsUsingGraphTraversals ................................ 48
4.2 AlgebraforAverage/RMSCurrentUpdates........................... 50
4.2.1 AlgebraforComputingAverageCurrent...................... 51
4.2.2 AlgebraforComputingtheRMSCurrent..................... 52
4.3 Results................................................................... 57
5 ExperimentalSetup.......................................................... 59
6 Results......................................................................... 63
6.1 TheElectromigrationEffectsforDifferentLogicGates.............. 81
6.1.1 NAND2_X2andNOR2_X2Gates ............................ 82
6.1.2 AOI21_X2....................................................... 85
6.1.3 NOR2_X4....................................................... 87
6.1.4 INV_X16........................................................ 88
6.2 Conclusion .............................................................. 91
7 AnalyzingtheElectromigrationEffectsonDifferentMetal
LayersandDifferentWireLengths........................................ 93
7.1 ExperimentalSetup ..................................................... 94
7.2 SimulationResults...................................................... 95
7.3 Conclusion .............................................................. 98
8 Conclusions................................................................... 99
8.1 FutureWorks............................................................ 100
A Impact on Physical Synthesis Considering Different
AmountsofInstanceswithEMAwareness................................ 103
B CouplingCapacitanceCurrents............................................ 111
References..................................................................... 113
List of Figures
Fig.1.1 A CMOS circuitcanfailfromspatialortemporal
unreliabilityeffects ................................................... 3
Fig.1.2 Expecteddevelopmentof currentdensities(J )
max
neededfordrivingfourinvertergates,accordingto
ITRS2011(seealsoTable1.1).EMdegradationneeds
tobeconsideredwhencrossingtheyellowbarrierof
currentdensities(J ).Asofnow,manufacturable
EM
solutionsarenotknownintheredarea ............................. 5
Fig.1.3 Evolutionoflifetimeversustechnologynode.Black
lineshowstheeffectofreducedcriticalvoidvolume:
GreenlineshowstheEMenhancementurgentlyneeded
(ITRS2011)........................................................... 5
Fig.1.4 Problem space: (a) currentsource modelingfor
signal-EM analysis and (b) load abstraction for
cell-internalEManalysis............................................. 6
Fig.1.5 (a) Thelayoutandoutputpinpositionoptionsfor
INV_X4.Charge/dischargecurrentswhentheoutput
pinisat(b)node4and(c)node3.Thered[blue]lines
representrise[fall]currents.(d)TheVddpinposition
optionsforINV_X4andthecurrentswhentheVddpin
isatnode30 and(e)node20.(f)TheVsspinposition
optionsforINV_X4andthecurrentswhentheVsspin
isatnode400and(g)node100......................................... 8
Fig.2.1 Standard-cellbasedsynthesisflow................................... 12
Fig.2.2 Flowdiagramimplementingprocessesproposed................... 14
Fig.2.3 Synthesis-analysisloopsinthedesignflowfordigital
circuits.Thecriticalsteps—physicalsynthesis(a)and
analysis(b)—areshown,supplementedbyoptionsto
addresscurrentdensityandotherelectromigration
issues(c) .............................................................. 15
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