Table Of ContentEDA for IC Implementation,
Circuit Design, and
Process Technology
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Electronic Design Automation for
Integrated Circuits Handbook
Edited by
Louis Scheffer, Luciano Lavagno,
and Grant Martin
EDA for IC System Design, Verification,
and Testing
EDA for IC Implementation, Circuit Design, and
Process Technology
EDA for IC Implementation,
Circuit Design, and
Process Technology
Edited by
Louis Scheffer
Cadence Design Systems
San Jose, California, U.S.A.
Luciano Lavagno
Cadence Berkeley Laboratories
Berkeley, California, U.S.A.
Grant Martin
Tensilica Inc.
Santa Clara, California, U.S.A.
Published in 2006 by
CRC Press
Taylor & Francis Group
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Boca Raton, FL 33487-2742
© 2006 by Taylor & Francis Group, LLC
CRC Press is an imprint of Taylor & Francis Group
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International Standard Book Number-10: 0-8493-7924-5 (Hardcover)
International Standard Book Number-13: 978-0-8493-7924-6 (Hardcover)
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Library of Congress Cataloging-in-Publication Data
EDA for IC implementation, circuit design, and process technology / editors, Louis Scheffer, Luciano
Lavagno, Grant Martin.
p. cm. -- (Electronic design automation for integrated circuits handbook)
Includes bibliographical references and index.
ISBN 0-8493-7924-5
1. Integrated circuits--Computer-aided design. 2. Integrated circuits--Design and construction. I. Title:
Electronic design automation for integrated circuit implementation, circuit design, and process technology.
II. Scheffer, Louis. III. Lavagno, Luciano, 1959- IV. Martin, Grant (Grant Edmund) V. Series.
TK7874.E257 2005
621.3815--dc22 2005052941
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Acknowledgments
and Dedication for the
EDA Handbook
The editors would like to acknowledge the unsung heroes ofEDA,those who work to advance the field
in addition to their own personal,corporate,or academic agendas.These men and women serve in a vari-
ety ofways — they run the smaller conferences,they edit technical journals,and they serve on standards
committees,just to name a few.These largely volunteer jobs won’t make anyone rich or famous despite
the time and effort that goes into them,but they do contribute mightily to the remarkable and sustained
advancement ofEDA.Our kudos to these folks,who don’t get the credit they deserve.
On a more personal note,Louis Scheffer would like to acknowledge the love,support,encouragement,
and help ofhis wife Lynde,his daughter Lucynda,and his son Loukos.Without them this project would
not have been possible.
Luciano Lavagno would like to thank his wife Paola and his daughter Alessandra Chiara for making his
life so wonderful.
Grant Martin would like to acknowledge,as always,the love and support ofhis wife,Margaret Steele,
and his two daughters,Jennifer and Fiona.
Preface
Preface for Volume 2
Electronic Design Automation (EDA) is a spectacular success in the art ofengineering.Over the last quar-
ter ofa century,improved tools have raised designers’productivity by a factor ofmore than a thousand.
Without EDA,Moore’s law would remain a useless curiosity.Not a single billion-transistor chip could be
designed or debugged without these sophisticated tools,so without EDA we would have no laptops,cell
phones,video games,or any ofthe other electronic devices we take for granted.
But spurred on by the ability to build bigger chips,EDA developers have largely kept pace,and these
enormous chips can still be designed,debugged,and tested,-and in fact,with decreasing time to market.
The story ofEDA is much more complex than the progression ofintegrated circuit (IC) manufactur-
ing,which is based on simple physical scaling ofcritical dimensions.Instead,EDA evolves by a series of
paradigm shifts.Every chapter in this book,all 49 of them,was just a gleam in some expert’s eye just a
few decades ago.Then it became a research topic,then an academic tool,and then the focus ofa startup
or two.Within a few years,it was supported by large commercial EDA vendors,and is now part of the
conventional wisdom. Although users always complain that today’s tools are not quite adequate for
today’s designs,the overall improvements in productivity have been remarkable.After all,in what other
field do people complain of onlya 21% compound annual growth in productivity,sustained over three
decades,as did the International Technology Roadmap for Semiconductors in 1999?
And what is the future ofEDA tools? As we look at the state ofelectronics and integrated circuit design
in the 2005–2006 timeframe,we see that we may soon enter a major period ofchange in the discipline.The
classical scaling approach to integrated circuits,spanning multiple orders ofmagnitude in the size ofdevices
over the last 40(cid:1)years,looks set to last only a few more generations or process nodes (though this has been
argued many times in the past, and has invariably been proved to be too pessimistic a projection).
Conventional transistors and wiring may well be replaced by new nano and biologically-based technologies
that we are currently only beginning to experiment with.This profound change will surely have a consider-
able impact on the tools and methodologies used to design integrated circuits.Should we be spending our
efforts looking at CAD for these future technologies,or continue to improve the tools we currently use?
Upon further consideration,it is clear that the current EDA approaches have a lot oflife left in them.
With at least a decade remaining in the evolution ofcurrent design approaches,and hundreds ofthou-
sands or millions ofdesigns left that must either craft new ICs or use programmable versions ofthem,it
is far too soon to forget about today’s EDA approaches.And even ifthe technology changes to radically
new forms and structures,many oftoday’s EDA concepts will be reused and evolved for design into tech-
nologies well beyond the current scope and thinking.
The field ofEDA for ICs has grown well beyond the point where any single individual can master it all,
or even be aware ofthe progress on all fronts.Therefore,there is a pressing need to create a snapshot of
this extremely broad and diverse subject.Students need a way oflearning about the many disciplines and
topics involved in the design tools in widespread use today.As design grows multi-disciplinary,electronics
designers and EDA tool developers need to broaden their scope.The methods used in one subtopic may
well have applicability to new topics as they arise.All of electronics design can utilize a comprehensive
reference work in this field.
Preface
With this in mind,we invited many experts from across all the disciplines involved in EDA to contribute
chapters summarizing and giving a comprehensive overview oftheir particular topic or field.As might be
appreciated,such chapters represent a snapshot ofthe state ofthe art,written in 2004–2005.However,as
surveys and overviews,they retain a lasting educational and reference value that will be useful to students
and practitioners for many years to come.
With a large number oftopics to cover,we decided to split the Handbook into two volumes.Volume 1
covers system-level design,micro-architectural design,and verification and test.Volume 2 covers the clas-
sical “RTL to GDS II”design flow,incorporating synthesis,placement and routing,along with related top-
ics;analog and mixed-signal design,physical verification,analysis and extraction,and technology CAD
topics.These roughly correspond to the classical “front-end/back-end”split in IC design,where the front
end (or logical design) focuses on making sure that the design does the right thing,assuming it can be
implemented, and the back-end (or physical design) concentrates on generating the detailed tooling
required,while taking the logical function as given.Despite limitations,this split has persisted through
the years — a complete and correct logical design,independent ofimplementation,remains an excellent
handoffpoint between the two major portions ofan IC design flow.Since IC designers and EDA devel-
opers often concentrate on one side ofthis logical/physical split,this seemed to be a good place to divide
the book as well.
Volume II opens with an overview ofthe classical RTL to GDS II design flows,and then steps imme-
diately into the logic synthesis aspect of“synthesis,place and route.”Power analysis and optimization
methods recur at several stages in the flow.Recently,equivalence checking has increased the reliability and
automation possible in the standard IC flows.We then see chapters on placement and routing and asso-
ciated topics ofstatic timing analysis and structured digital design.The standard back end flow relies on
standard digital libraries and design databases,and must produce IC designs that fit well into packages
and onto boards and hybrids.The relatively new emphasis on design closure knits many aspects of the
flow together.Indeed,chapter 10,on design closure,is a good one to read right after Chapter 1,on design
flows.
Before diving into the area of analog and mixed-signal design, the handbook looks at the special
methods appropriate to FPGA design-this is a growing area for rapid IC design using underlying fixed
but reprogrammable platforms. Then we turn to analog design, where we cover simulation methods,
advanced modeling, and layout tools. Physical verification, analysis and extraction covers design rule
checking,transformation ofdesigns for manufacturability,analysis ofpower supply noise and other noise
issues,and layout extraction.Finally,the handbook looks at process simulation and device modeling,and
advanced parasitic extraction as aspects oftechnology CAD for ICs.
This handbook with its two constituent constitutes a valuable learning and reference work for every-
one involved and interested in learning about electronic design and its associated tools and methods.We
hope that all readers will find it ofinterest and a well-thumbed resource.
Louis Scheffer
Luciano Lavagno
Grant Martin
San Jose,Berkeley,and Santa Clara
Editors
Louis Scheffer
Louis Scheffer received the B.S. and M.S. degrees from Caltech in 1974 and 1975, and a Ph.D. from
Stanford in 1984.He worked at Hewlett Packard from 1975 to 1981 as a chip designer and CAD tool
developer.In 1981,he joined Valid Logic Systems,where he did hardware design,developed a schematic
editor,and built an IC layout,routing,and verification system.In 1991,Valid merged with Cadence,and
since then he has been working on place and route,floorplanning systems,and signal integrity issues.
His main interests are floorplanning and deep sub-micron effects. He has written many technical
papers,tutorials,invited talks and panels,and has served the conferences DAC,ICCAD,ISPD,SLIP,and
TAU as a technical committee member.He is currently the general chair of TAU and ISPD,and on the
steering committee ofSLIP.He holds five patents in the field ofEDA,and has taught courses on CAD for
electronics at Berkeley and Stanford.He is also interested in SETI,and serves on the technical advisory
board for the Allen Telescope Array at the SETI institute,and is a co-author of the book SETI-2020,in
addition to several technical articles in the field.
Luciano Lavagno
Luciano Lavagno received his Ph.D.in EECS from U.C.Berkeley in 1992 and from Politecnico di Torino
in 1993.He is a co-author oftwo books on asynchronous circuit design,ofa book on hardware/software
co-design ofembedded systems,and ofover 160 scientific papers.
Between 1993 and 2000, he was the architect of the POLIS project, a cooperation between U.C.
Berkeley,Cadence Design Systems,Magneti Marelli and Politecnico di Torino,which developed a com-
plete hardware/software co-design environment for control-dominated embedded systems.
He is currently an Associate Professor with Politecnico di Torino,Italy and a research scientist with
Cadence Berkeley Laboratories.He is serving on the technical committees of several international con-
ferences in his field (e.g.DAC,DATE,ICCAD,ICCD) and of various workshops and symposia.He has
been the technical program and tutorial chair ofDAC,and the TPC and general chair ofCODES.He has
been associate and guest editor of IEEE Transactions on CAD, IEEE Transactions on VLSI and ACM
Transactions on Embedded Computing Systems.
His research interests include the synthesis of asynchronous and low-power circuits,the concurrent
design of mixed hardware and software embedded systems, and compilation tools and architectural
design ofdynamically reconfigurable processors.
Grant Martin
Grant Martin is a chiefscientist at Tensilica,Inc.in Santa Clara,California.Before that,Grant worked for
Burroughs in Scotland for 6 years;Nortel/BNR in Canada for 10 years;and Cadence Design Systems for
9 years, eventually becoming a Cadence Fellow in their Labs. He received his Bachelor’s and Master’s
degrees in Mathematics (Combinatorics and Optimization) from the University ofWaterloo,Canada,in
1977 and 1978.
