DUAL CHANNEL 14-BITS 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS (Rev. C)

78 Pages·2014·1.85 MB·English

ADS62P45, ADS62P44
ADS62P43, ADS62P42
www.ti.com SLAS561C–JULY2007–REVISEDFEBRUARY2012
DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
CheckforSamples:ADS62P45,ADS62P44,ADS62P43,ADS62P42
FEATURES • Medical Imaging
1
• MaximumSampleRate:125MSPS • RadarSystems
• 14-BitResolutionwithNoMissingCodes • TestandMeasurementInstrumentation
• 95dBCrosstalk
DESCRIPTION
• ParallelCMOSand DDRLVDS OutputOptions
ADS62P4X is a dual channel 14-bit A/D converter
• 3.5dBCoarseGainandProgrammableFine
family with maximum sample rates up to 125 MSPS.
Gainupto6dBforSNR/SFDR Trade-Off It combines high performance and low power
• DigitalProcessingBlockwith: consumption in a compact 64 QFN package. Using
an internal sample and hold and low jitter clock
– OffsetCorrection
buffer, theADCsupportshighSNRandhigh SFDRat
– FineGainCorrection,inStepsof0.05dB
high input frequencies. It has coarse and fine gain
– Decimationby2/4/8 options that can be used to improve SFDR
performanceatlowerfull-scaleinput ranges.
– Built-inandCustom Programmable24-Tap
Low-/High-/Band-PassFilters ADS62P4X includes a digital processing block that
• SupportsSine,LVPECL,LVDS and LVCMOS consists of several useful and commonly used digital
ClocksandAmplitudeDownto400mV functions such as ADC offset correction, fine gain
PP
correction (in steps of 0.05 dB), decimation by 2,4,8
• ClockDutyCycleStabilizer
and in-built and custom programmable filters. By
• InternalReference;SupportsExternal default, the digital processing block is bypassed, and
Referencealso itsfunctionsaredisabled.
• 64-QFNPackage(9mm×9mm) Two output interface options exist – parallel CMOS
• PinCompatible12-BitFamily(ADS62P2X) and DDR LVDS (Double Data Rate). ADS62P4X
includes internal references while traditional
APPLICATIONS reference pins and associated decoupling capacitors
have been eliminated. Nevertheless, the device can
• WirelessCommunicationsInfrastructure
also be driven with an external reference. The device
• SoftwareDefinedRadio is specified over the industrial temperature range
(–40°Cto85°C).
• PowerAmplifier Linearization
• 802.16d/e
Table1.ADS62P4XPerformanceSummary
ADS62P45 ADS62P44 ADS62P43 ADS62P42
F =10MHz(0dBgain) 88 92 93 94
in
SFDR,dBc
F =190MHz(3.5dBgain) 84 86 87 85
in
F =10MHz(0dBgain) 73.7 74.2 74.6 74.7
in
SINAD,dBFS
F =190MHz(3.5dBgain) 70.8 71 71.3 70.9
in
AnalogPower,mW 799 710 594 515
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas
Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2007–2012,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarilyincludetestingofallparameters.
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ADS62P43, ADS62P42
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore
susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.
D D
D D D N
D N V G
V G R R
A A D D
Digital Processing DA0
Block DA1
DA2
ChannelA DA3
DA4
INA_P Output DA5
Digital Buffers DA6
SHA 14-BitADC
INA_M Encoder DA7
14 Bit 14 Bit ChannelA DA8
DA9
DA10
DA11
DA12
DA13
CLKP Output Clock
CLOCKGEN CLKOUT
CLKM Buffer
DB0
DB1
DB2
DB3
DB4
INB_P 14 Bit 14 Bit Output DB5
Digital Buffers DB6
SHA 14-BitADC
INB_M Encoder DB7
Channel B DB8
Digital Processing DB9
Block DB10
DB11
DB12
Channel B
DB13
VCM Reference Control Interface
CMOSInterface
RESETSCLKSENDAATA CTRL1CTRL2CTRL3
S
B0286-01
ADS62PXXFamily
125MSPS 105MSPS 80MSPS 65MSPS
ADS62P4X
ADS62P45 ADS62P44 ADS62P43 ADS62P42
14Bits
ADS62P2X
ADS62P25 ADS62P24 ADS62P23 ADS62P22
12Bits
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PACKAGE/ORDERINGINFORMATION(1)
SPECIFIED
PACKAGE- PACKAGE PACKAGE ORDERING TRANSPORTMEDIA,
PRODUCT TEMPERATURE
LEAD DESIGNATOR MARKING NUMBER QUANTITY
RANGE
ADS62P45IRGCT TapeandReel,250
ADS62P45 QFN-64(2) RGC –40°Cto85°C AZ62P45
ADS62P45IRGCR TapeandReel,2500
ADS62P44IRGCT TapeandReel,250
ADS62P44 QFN-64(2) RGC –40°Cto85°C AZ62P44
ADS62P44IRGCR TapeandReel,2500
ADS62P43IRGCT TapeandReel,250
ADS62P43 QFN-64(2) RGC –40°Cto85°C AZ62P43
ADS62P43IRGCR TapeandReel,2500
ADS62P42IRGCT TapeandReel,250
ADS62P42 QFN-64(2) RGC –40°Cto85°C AZ62P42
ADS62P42IRGCR TapeandReel,2500
(1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI
websiteatwww.ti.com.
(2) Forthermalpadsizeonthepackage,seethemechanicaldrawingsattheendofthisdatasheet.θ =23.17°C/W(0LFMairflow),
JA
θ =22.1°C/Wwhenusedwith2oz.coppertraceandpadsoldereddirectlytoaJEDECstandardfourlayer3in×3in(7.62cm×
JC
7.62cm)PCB.
ABSOLUTE MAXIMUM RATINGS(1)
VALUE UNIT
Supplyvoltagerange,AVDD –0.3to3.9 V
V
I
Supplyvoltagerange,DRVDD –0.3to3.9 V
VoltagebetweenAGNDandDRGND –0.3to0.3 V
VoltagebetweenAVDDtoDRVDD –0.3to3.3 V
VoltageappliedtoVCMpin(inexternalreferencemode) –0.3to2 V
Voltageappliedtoanaloginputpins,INPandINM –0.3tominimum(3.6,AVDD+0.3) V
Voltageappliedtoanaloginputpins,CLKPandCLKM –0.3to(AVDD+0.3) V
T Operatingfree-airtemperaturerange –40to85 °C
A
T Operatingjunctiontemperaturerange 125 °C
J
T Storagetemperaturerange –65to150 °C
stg
(1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings
only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating
conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
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RECOMMENDED OPERATING CONDITIONS
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
MIN NOM MAX UNIT
SUPPLIES
AVDD Analogsupplyvoltage 3 3.3 3.6 V
CMOSinterface 1.65 1.8to3.3 3.6 V
DRVDD Outputbuffersupplyvoltage (1)
LVDSinterface 3 3.3 3.6 V
ANALOGINPUTS
Differentialinputvoltagerange 2 V
pp
V Inputcommon-modevoltage 1.5±0.1 V
IC
VoltageappliedonVCMinexternalreferencemode 1.45 1.5 1.55 V
CLOCKINPUT
ADS62P45 1 125
ADS62P44 1 105
Inputclocksamplerate,F MSPS
S
ADS62P43 1 80
ADS62P42 1 65
Sinewave,ac-coupled 0.4 1.5
Inputclockamplitudedifferential LVPECL,ac-coupled ±0.8
V
(VCLKP–VCLKM) LVDS,ac-coupled ±0.35 pp
LVCMOS,ac-coupled 3.3
Inputclockdutycycle 35% 50% 65%
DIGITALOUTPUTS
DEFAULT
forC ≤5pFandDRVDD≥2.2V
LOAD strength
Outputbufferdrivestrength (2) forC >5pFandDRVDD≥2.2V MAXIMUM
LOAD strength
MAXIMUM
forDRVDD<2.2V
strength
CMOSinterface,maximumbuffer 10
strength
Maximumexternalloadcapacitancefromeach LVDSinterface,withoutinternal 5
C pF
LOAD outputpintoDRGND termination
LVDSinterface,withinternal 10
termination
R Differentialloadresistance(external)betweentheLVDSoutputpairs 100 Ω
LOAD
T Operatingfree-airtemperature -40 85 °C
A
(1) Foreasymigrationtothenextgeneration,highersamplingspeeddevices(>125MSPS),use1.8VDRVDDsupply.
(2) SeeOutputBufferStrengthProgrammabilityinapplicationsection.
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ELECTRICAL CHARACTERISTICS
Typicalvaluesareat25°C,AVDD=3.3V,DRVDD=1.8vto3.3V,maximumratedsamplingfrequency,50%clockduty
cycle,–1dBFSdifferentialanaloginput,internalreferencemode,appliestoCMOSandLVDSinterfaces,unlessotherwise
noted.
MinandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=3.3V,DRVDD=3.3V,
MIN MAX
unlessotherwisenoted.
ADS62P45 ADS62P44 ADS62P43 ADS62P42
PARAMETER FS=125MSPS FS=105MSPS FS=80MSPS FS=65MSPS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
RESOLUTION 14 14 14 14 Bits
ANALOGINPUT
Differentialinputvoltagerange 2 2 2 2 VPP
Differentialinputresistance(dc)
>1 >1 >1 >1 MΩ
seeFigure84
Differentialinputcapacitance
7 7 7 7 pF
seeFigure85
Analoginputbandwidth 450 450 450 450 MHz
Analoginputcommonmodecurrent(per μA/MSP
1.3 1.3 1.3 1.3
inputpinofeachADC) S
REFERENCEVOLTAGES
VREFB Internalreferencebottomvoltage 1 1 1 1 V
VREFT Internalreferencetopvoltage 2 2 2 2 V
VCM Commonmodeoutputvoltage 1.5 1.5 1.5 1.5 V
VCMoutputcurrentcapability 4 4 4 4 mA
DCACCURACY
Nomissingcodes Specified Specified Specified Specified
EO Offseterror -10 ±2 10 -10 ±2 10 -10 ±2 10 -10 ±2 10 mV
Offseterrortemperaturecoefficient 0.05 0.05 0.05 0.05 mV/°C
Therearetwosourcesofgainerror–internalreferenceinaccuracyandchannelgainerror
EGREF Gainerrorduetointernalreference -2 0.25 2 -2 0.25 2 -2 0.25 2 -2 0.25 2 %FS
inaccuracyalone
EGCHAN Gainerrorofchannelalone(1)
acrossdevices&acrosschannelswithina -1 ±0.3 1 -1 ±0.3 1 -1 ±0.3 1 -1 ±0.3 1 %FS
device.
0.00
Channelgainerrortemperaturecoefficient 0.005 0.005 0.005 Δ%/°C
5
- ± -
DNL Differentialnonlinearity -0.95 ±0.6 -0.95 ±0.6 ±0.5 LSB
0.95 0.5 0.95
INL Integralnonlinearity -5 ±2.5 5 -5 ±2.5 5 -5 ±2 5 -5 ±2 5 LSB
POWERSUPPLY
IAVDD Analogsupplycurrent 240 275 215 240 180 200 156 175 mA
Digitalsupplycurrent, Noexternalload 17 14 12 10 mA
CMOSinterface capacitance
IDRVDD DRVDD=1.8V 10-pFexternal
Fin=2MHz(2) loadcapacitance 30 26 22 19 mA
Digitalsupplycurrent,LVDSinterface
IDRVDD with100-Ωexternaltermination 73 73 73 73 mA
PAVDD Analogpowerdissipation 799 908 710 792 594 660 515 578 mW
Noexternalload
Digitalpowerdissipation, capacitance 31 25 22 18 mW
PDRVDD CMOSinterface
DRVDD=1.8V(3) 10-pFexternal 54 47 40 34 mW
loadcapacitance
Globalpowerdown 50 75 50 75 50 75 50 75 mW
(1) Thisisspecifiedbydesignandcharacterization;itisnottestedinproduction.
(2) InCMOSmode,theDRVDDcurrentscaleswiththesamplingfrequency,theloadcapacitanceonoutputpins,inputfrequencyandthe
supplyvoltage(seeFigure81andCMOSpowerdissipationinapplicationsection).
(3) ThemaximumDRVDDcurrentdependsontheactualloadcapacitanceonthedigitaloutputlines.Notethatthemaximum
recommendedloadcapacitanceoneachdigitaloutputlineis10pF.
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ELECTRICAL CHARACTERISTICS
Typicalvaluesareat25°C,AVDD=3.3V,DRVDD=1.8Vto3.3V,maximumratedsamplingfrequency,50%clockduty
cycle,–1dBFSdifferentialanaloginput,internalreferencemode,appliestoCMOSandLVDSinterfaces,unlessotherwise
noted.
MinandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=3.3V,DRVDD=3.3V,
MIN MAX
unlessotherwisenoted.
ADS62P45 ADS62P44 ADS62P43 ADS62P42
PARAMETER TESTCONDITIONS FS=125MSPS FS=105MSPS FS=80MSPS FS=65MSPS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
DYNAMICACCHARACTERISTICS
Fin=10MHz 74.2 74.5 74.8 74.8
Fin=50MHz 70 73.9 74.2 71 74.4 74.5
SNR
Fin=70MHz 73.6 70 74 73.9 71 74.1
Signaltonoise dBFS
ratio 0dBgain 72.3 72.3 72.5 72.2
Fin=190
MHz 3.5dBcoarse 71 71.2 71.6 70.8
gain
RMSOutput
Inputstiedtocommon-mode 1.0 1.0 1.0 1.0 LSB
Noise
Fin=10MHz 73.7 74.2 74.6 74.7
Fin=50MHz 69 73.3 73.5 70 74.2 74.3
SINAD
Signaltonoise Fin=70MHz 73.2 69 73.5 73.8 70 73.9
dBFS
anddistortion
0dBgain 71.4 71.8 72 71.5
ratio Fin=190
MHz 3.5dBcoarse 70.8 71 71.3 70.9
gain
ENOB Fin=50MHz 11.2 11.9 11.3 12
Effective Bits
NumberofBits Fin=70MHz 11.2 11.95 11.3 12
Fin=10MHz 88 92 93 94
Fin=50MHz 76 80 83 78 87 87
SFDR
Fin=70MHz 86 78 85 89 79 89
SpuriousFree dBc
DynamicRange 0dBgain 81 83 83 81
Fin=190
MHz 3.5dBcoarse 84 86 87 85
gain
Fin=10MHz 88 90 92 93
Fin=50MHz 73 79 82 76 86 86
THD
Fin=70MHz 84.5 75 84 88 76 88
TotalHarmonic dBc
Distortion 0dBgain 79 80 80 79
Fin=190
MHz 3.5dBcoarse 81 82 82 82
gain
Fin=10MHz 94 93 95 98
Fin=50MHz 76 92 93 78 94 97
HD2
Second Fin=70MHz 92 78 93 94 79 96
dBc
Harmonic
0dBgain 86 86 85 86
Distortion Fin=190
MHz 3.5dBcoarse 88 88 88 89
gain
Fin=10MHz 88 92 93 94
Fin=50MHz 76 80 83 78 87 87
HD3
Fin=70MHz 86 78 85 89 79 89
ThirdHarmonic dBc
Distortion 0dBgain 81 83 83 81
Fin=190
MHz 3.5dBcoarse 84 86 87 85
gain
Fin=10MHz 95 96 97 99
WorstSpur Fin=50MHz 94 95 96 98
(Otherthan dBc
HD2,HD3) Fin=70MHz 94 95 96 97
Fin=190MHz 90 93 95 92
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ELECTRICAL CHARACTERISTICS (continued)
Typicalvaluesareat25°C,AVDD=3.3V,DRVDD=1.8Vto3.3V,maximumratedsamplingfrequency,50%clockduty
cycle,–1dBFSdifferentialanaloginput,internalreferencemode,appliestoCMOSandLVDSinterfaces,unlessotherwise
noted.
MinandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=3.3V,DRVDD=3.3V,
MIN MAX
unlessotherwisenoted.
ADS62P45 ADS62P44 ADS62P43 ADS62P42
PARAMETER TESTCONDITIONS FS=125MSPS FS=105MSPS FS=80MSPS FS=65MSPS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
IMD
2-Tone F1=185MHz,F2=190MHz
88 87 92 92 dBFS
Intermodulation eachtoneat-7dBFS
Distortion
Crosstalk Upto100MHz 95 95 95 95 dB
Recoverytowithin1%(offinal
InputOverload clock
value)for6-dBoverloadwithsine 1 1 1 1
Recovery cycles
waveinput
PSRR
ACPower for100mVppsignalonAVDD
35 35 35 35 dBc
Supply supply
RejectionRatio
DIGITAL CHARACTERISTICS(1)
TheDCspecificationsrefertotheconditionwherethedigitaloutputsarenotswitching,butarepermanentlyatavalidlogic
level0or1,AVDD=3.0Vto3.6V.
ADS62P45/ADS62P44
PARAMETER TESTCONDITIONS
ADS62P43/ADS62P42
MIN TYP MAX UNIT
DIGITALINPUTS
RESET,CTRL1,CTRL2,CTRL3,SCLK,SDATA&SEN (2)
High-levelinputvoltage 2.4 V
Low-levelinputvoltage 0.8 V
High-levelinputcurrent 33 μA
Low-levelinputcurrent –33 μA
Inputcapacitance 4 pF
DIGITALOUTPUTS
CMOSINTERFACE,DRVDD=1.65Vto3.6V
High-leveloutputvoltage DRVDD V
Low-leveloutputvoltage 0 V
Outputcapacitanceinsidethedevice,from
Outputcapacitance 2 pF
eachoutputtoground
DIGITALOUTPUTS
LVDSINTERFACE,DRVDD=3.0Vto3.6V,I =3.5mA,R =100Ω (3)
O L
High-leveloutputvoltage 1375 mV
Low-leveloutputvoltage 1025 mV
Outputdifferentialvoltage,|V | 225 350 mV
OD
V Outputoffsetvoltage,single-ended Common-modevoltageofOUTP,OUTM 1200 mV
OS
Outputcapacitanceinsidethedevice,from
Outputcapacitance 2 pF
eitheroutputtoground
(1) AllLVDSandCMOSspecificationsarecharacterized,butnottestedatproduction.
(2) SCLK&SENfunctionasdigitalinputpinswhentheyareusedforserialinterfaceprogramming.Whenusedasparallelcontrolpins,
analogvoltageneedstobeappliedasperTable4&Table5
(3) I referstotheLVDSbuffercurrentsetting,R isthedifferentialloadresistancebetweentheLVDSoutputpair.
O L
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TIMING CHARACTERISTICS – LVDS AND CMOS MODES(1)
Typicalvaluesarespecifiedat25°C,AVDD=DRVDD=3.3V,maximumratedsamplingfrequency,sinewaveinputclock,
1.5V clockamplitude,C =5pF(2),I =3.5mA,R =100Ω(3),nointernaltermination,unlessotherwisenoted.
PP L O L
MinandmaxvaluesarespecifiedacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=3.0Vto3.6V,
MIN MAX
unlessotherwisespecified.
ADS62P45 ADS62P44 ADS62P43 ADS62P42
PARAMETER TESTCONDITIONS FS=125MSPS FS=105MSPS FS=80MSPS FS=65MSPS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
Aperture
ta delay 0.7 1.5 2.5 0.7 1.5 2.5 0.7 1.5 2.5 0.7 1.5 2.5 ns
|ta1-ta2|,
Channel-to-channel
50 50 50 50
withinthesame
Aperture device
delay ps
matching |ta1-ta2|,
Channel-to-channel
450 450 450 450
acrosstwodevicesat
sametemperature
Aperture
tj jitter 150 150 150 150 fsrms
fromglobalpower
15 50 15 50 15 50 15 50 μs
down
Wake-up
time fromstandby 15 50 15 50 15 50 15 50 μs
(tovalid
fromoutput CMOS 100 200 100 200 100 200 100 200 ns
data)
buffer
disable LVDS 200 500 200 500 200 500 200 500 ns
default,afterreset 14 14 14 14 clockcycles
withlowlatencymode
10 10 10 10 clockcycles
Latency enabled
withdecimationfilter
15 15 15 15 clockcycles
enabled
DDRLVDSMODE(4),DRVDD=3.0Vto3.6V
Datavalid(6)to
Datasetup
tsu time(5) zero-crossof 0.6 1.5 1.0 2.3 2.4 3.8 3.8 5.2 ns
CLKOUTP
Zero-crossof
Datahold
th time(5) CbeLcKoOmUinTgPintovadliadt(a6) 1.0 2.3 1.0 2.3 1.0 2.3 1.0 2.3 ns
Inputclockrisingedge
Clock
zero-crosstooutput
tPDI propagation clockrisingedge 3.5 5.5 7.5 3.5 5.5 7.5 3.5 5.5 7.5 3.5 5.5 7.5 ns
delay
zero-cross
Dutycycleof
LVDSbit differentialclock,
clockduty (CLKOUTP- 46% 50% 53% 46% 50% 53% 46% 50% 53% 46% 50% 53%
cycle CLKOUTM)
10≤Fs≤125MSPS
Risetimemeasured
from–50mVto50
Datarise
mV
tr time Falltimemeasured 70 100 170 70 100 170 70 100 170 70 100 170 ps
tf Datafall from50mVto–50
time
mV
1≤Fs≤125MSPS
Risetimemeasured
from–50mVto50
Outputclock
mV
tCLKRISE risetime Falltimemeasured 70 100 170 70 100 170 70 100 170 70 100 170 ps
tCLKFALL Outputclock from50mVto–50
falltime
mV
1≤Fs≤125MSPS
(1) Timingparametersarespecifiedbydesignandcharacterizationandnottestedinproduction.
(2) C istheeffectiveexternalsingle-endedloadcapacitancebetweeneachoutputpinandground.
L
(3) I referstotheLVDSbuffercurrentsetting;R isthedifferentialloadresistancebetweentheLVDSoutputpair.
O L
(4) Measurementsaredonewithatransmissionlineof100-Ωcharacteristicimpedancebetweenthedeviceandtheload.
(5) Setupandholdtimespecificationstakeintoaccounttheeffectofjitterontheoutputdataandclock.
(6) Datavalidreferstologichighof+100mVandlogiclowof–100mV.
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TIMING CHARACTERISTICS – LVDS AND CMOS MODES(1) (continued)
Typicalvaluesarespecifiedat25°C,AVDD=DRVDD=3.3V,maximumratedsamplingfrequency,sinewaveinputclock,
1.5V clockamplitude,C =5pF(2),I =3.5mA,R =100Ω(3),nointernaltermination,unlessotherwisenoted.
PP L O L
MinandmaxvaluesarespecifiedacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=3.0Vto3.6V,
MIN MAX
unlessotherwisespecified.
ADS62P45 ADS62P44 ADS62P43 ADS62P42
PARAMETER TESTCONDITIONS FS=125MSPS FS=105MSPS FS=80MSPS FS=65MSPS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
PARALLELCMOSMODE,DRVDD=2.5Vto3.6V,defaultoutputbufferdrivestrength(7)
Datasetup Datavalid(8)to50%of
tsu time(5) CLKOUTrisingedge 2.0 3.5 2.8 4.3 4.3 5.8 5.7 7.2 ns
50%ofCLKOUT
Datahold
th time(5) rbiseicnogmeindggeintvoadliadt(a8) 2.0 3.5 2.7 4.2 4.2 5.7 5.6 7.1 ns
Clock Inputclockrisingedge
tPDI propagation zero-crossto50%of 5.8 7.3 8.8 5.8 7.3 8.8 5.8 7.3 8.8 5.8 7.3 8.8 ns
delay CLKOUTrisingedge
Dutycycleofoutput
Outputclock
clock(CLKOUT) 45% 53% 60% 45% 53% 60% 45% 53% 60% 45% 53% 60%
dutycycle
10≤Fs≤125MSPS
Risetimemeasured
from20%to80%of
Datarise
DRVDD
tr time Falltimemeasured 1.0 1.8 2.5 1.0 1.8 2.5 1.0 1.8 2.5 1.0 1.8 2.5 ns
tf Datafall from80%to20%of
time
DRVDD
1≤Fs≤125MSPS
Risetimemeasured
from20%to80%of
Outputclock
DRVDD
tCLKRISE risetime Falltimemeasured 1.0 1.8 2.5 1.0 1.8 2.5 1.0 1.8 2.5 1.0 1.8 2.5 ns
tCLKFALL Outputclock from80%to20%of
falltime
DRVDD
1≤Fs≤125MSPS
PARALLELCMOSINTERFACE,DRVDD=1.8V,maximumbufferdrivestrength(9)
Inputclockrisingedge
tSTART Starttime todatagettingvalid 8.5 7.5 5.5 3.6 ns
(10)(11)
Widthofvaliddata
tDV window 3.3 6.0 5.0 7.5 8.0 10.5 10.5 13.5 ns
PARALLELCMOSINTERFACE,DRVDD=1.8V,MULTIPLEXEDMODE,maximumbufferdrivestrength
FS=65MSPS FS=40MSPS
UNIT
MIN TYP MAX MIN TYP MAX
Inputclockfalling
Starttime, edgetochannelA
tSTART_CHA channelA datagettingvalid(10) 0.8 2.3 –4.5 –3 ns
(11)
Datavalid, Widthofvaliddata
tDV_CHA channelA window 5.4 6.4 10.3 11.3 ns
Inputclockrisingedge
Starttime,
tSTART_CHB channelB tgoetcthinagnvnaellidB(d10a)ta(11) 1.1 2.4 –4.1 –2.5 ns
Datavalid, Widthofvaliddata
tDV_CHB channelB window 5 6 9.7 10.7 ns
(7) ForDRVDD<2.2V,itisrecommendedtouseexternalclockfordatacaptureandNOTthedeviceoutputclocksignal(CLKOUT).See
ParallelCMOSinterfaceinapplicationsection.
(8) Datavalidreferstologichighof2V(1.7V)andlogiclowof0.8V(0.7V)forDRVDD=3.3V(2.5V).
(9) ForDRVDD<2.2V,outputclockcannotbeusedfordatacapture.Adelayedversionoftheinputclockcanbeused,thatgivesthe
desiredsetup&holdtimesatthereceivingchip
(10) DatavalidreferstoLOGICHIGHof1.26VandLOGICLOWof0.54VforDRVDD=1.8V
(11) Measuredfromzero-crossingofinputclockhaving50%dutycycle
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Table2.TimingCharacteristicsatLowerSamplingFrequencies
Sampling
t CLOCKPROPAGATIONDELAY,
frequency, t DATASETUPTIME,ns t DATAHOLDTIME,ns PDI
su h ns
MSPS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
CMOSINTERFACE,DRVDD=2.5VTO3.6V
40 10.5 12 10.3 11.8
5.8 7.3 8.8
20 23 24.5 23 24.5
LVDSINTERFACE,DRVDD=3.0Vto3.6V
40 8.5 10 1 2.3
3.5 5.5 7.5
20 21 22.5 1 2.3
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