Dual Channel 11-Bits 125-MSPS ADC w/parallel CMOS / DDR LVDS Outputs datasheet

65 Pages·2017·1.46 MB·English

ADS62P15
www.ti.com SLAS572C–OCTOBER2007–REVISEDFEBRUARY2012
Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs
CheckforSamples:ADS62P15
FEATURES Referencealso
1
• MaximumSampleRate:125MSPS • 64-QFNPackage(9mm×9mm)
• 11-BitResolutionWithNoMissingCodes • PinCompatible14-bitand12-bitFamily
(ADS62P4X/ADS62P2X)
• 84dBcSFDRatFin=50MHz
• 67.1dBFSSNRatFin=50MHz
APPLICATIONS
• 92dBCrosstalk
• WirelessCommunicationsInfrastructure
• ParallelCMOSand DDRLVDS OutputOptions
• SoftwareDefinedRadio
• 3.5dBCoarseGainandProgrammableFine
• PowerAmplifier Linearization
Gainupto6dBforSNR/SFDR Trade-Off
• 802.16d/e
• DigitalProcessingBlockWith:
• Medical Imaging
– OffsetCorrection
• RadarSystems
– FineGainCorrection,inStepsof0.05dB
• TestandMeasurementInstrumentation
– Decimationby2/4/8
– Built-inandCustom Programmable24-Tap Table1.ADS62PXXDual ChannelFamily
Low/High/BandPassFilters
125MSPS 105MSPS 80MSPS 65MSPS
• SupportsSine,LVPECL,LVDS& LVCMOS
ADS62P4X
Clocks& AmplitudeDownto400mV ADS62P45 ADS62P44 ADS62P43 ADS62P42
PP (14bit)
• ClockDutyCycleStabilizer ADS62P2X
ADS62P25 ADS62P24 ADS62P23 ADS62P22
(12bit)
• InternalReference;SupportsExternal
(11bit) ADS62P15 - - -
DESCRIPTION
ADS62P15isadualchannel11-bitA/D converterwith maximumsampleratesupto125MSPS. It combineshigh
performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and
low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and
finegainoptionsthatcanbeusedtoimproveSFDRperformanceatlowerfull-scaleinput ranges.
ADS62P15 includes a digital processing block that consists of several useful and commonly used digital
functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and
in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions
aredisabled.
Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P15 includes
internal references while traditional reference pins and associated decoupling capacitors have been eliminated.
Nevertheless,thedevicecanalsobedrivenwithanexternalreference.Thedeviceisspecifiedoverthe industrial
temperaturerange(–40°Cto85°C).
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas
Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2007–2012,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarilyincludetestingofallparameters.
ADS62P15
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore
susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.
FUNCTIONALBLOCKDIAGRAM
D D
D D D N
D N V G
V G R R
A A D D
Digital Processing
Block
DA0
ChannelA DA1
DA2
Output DA3
INA_P Digital Buffers DA4
SHA 11-BitADC Encoder DA5
INA_M 11 Bit 11 Bit ChannelA DA6
DA7
DA8
DA9
DA10
Output
CLKP
CLOCKGEN Clock CLKOUT
CLKM
Buffer
DB0
DB1
DB2
DB3
INB_P 11 Bit 11 Bit Output DB4
SHA 11-BitADC Digital Buffers DB5
Encoder
INB_M DB6
Channel B
DB7
DB8
Digital Processing DB9
Block DB10
Channel B
Control
VCM Reference
Interface
CMOS INTERFACE
RESETSCLKSENSDATA CTRL1CTRL2CTRL3
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FromADC CLIPPER
output 11bits 11bits 11bits 11bits 11bits
To LVDS or CMOS
output buffers
FINE GAIN GAIN 24TAPFILTER
(0to6stdeBp,s0).5dB C(0O.0R5RdBE CstTeIpOsN) ---LBHOAIGWNHD P PPAAASSSSSS DECBIYM2A/4T/8ION 11bits
0 DISABLE
OFFSET
OFFSET CORRECTION FILTER
ESTIMATION SELECTION BYPASS
BLOCK FILTER
BYPASS
DECIMATION
FREEZE
OFFSET
CORRECTION
DIGITAL
PROCESSING BLOCK
Figure1. Digital ProcessingBlockDiagram
PACKAGE/ORDERINGINFORMATION(1)
PACKAGE- PACKAGE SPECIFIED LEAD/BALL PACKAGE ORDERING(2) TRANSPORT
PRODUCT TEMPERATURE MEDIA,
LEAD DESIGNATOR FINISH MARKING NUMBER
RANGE QUANTITY
ADS62P15RGCT 250Tape/Reel
ADS62P15 QFN-64 RGC –40°Cto85°C CuNiPdAu AZ62P15
ADS62P15RGCR 2000Tape/Reel
(1) Forthermalpadsizeonthepackage,seethemechanicaldrawingsattheendofthisdatasheet.θ =23.17°C/W(0LFMairflow),θ
JA JC
=22.1°C/Wwhenusedwith2oz.coppertraceandpadsoldereddirectlytoaJEDECstandardfourlayer3in.x3in.PCB.
(2) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI
websiteatwww.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
VALUE UNIT
Supplyvoltagerange,AVDD,DRVDD –0.3Vto3.9 V
–0.3Vto3.9 V
VoltagebetweenAGNDandDRGND –0.3to0.3 V
VoltagebetweenAVDDtoDRVDD –0.3to3.3 V
V
SS
Voltageappliedtoexternalpin,CM(inexternalreferencemode) -0.3to2 V
–0.3Vtominimum
Voltageappliedtoanaloginputpins,INA_P,INA_M,INB_P,INB_M V
(3.6,AVDD+0.3V)
Voltageappliedtoclockinputpins,CLKP,CLKM –0.3VtoAVDD+0.3V V
T Operatingfree-airtemperaturerange –40to85 °C
A
T Operatingjunctiontemperaturerange 125 °C
J
T Storagetemperaturerange –65to150 °C
stg
(1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings
onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating
conditionsisnotimplied.Exposuretoabsolutemaximumratedconditionsforextendedperiodsmayaffectdevicereliability.
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RECOMMENDED OPERATING CONDITIONS
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
MIN NOM MAX UNIT
SUPPLIES
Analogsupplyvoltage,AVDD 3 3.3 3.6 V
V CMOSinterface 1.65 1.8to3.3 3.6
SS
Digitalsupplyvoltage,DRVDD V
LVDSinterface 3.0 3.3 3.6
ANALOGINPUTS
Differentialinputvoltagerange 2 V
PP
Inputcommon-modevoltage 1.5±0.1 V
VoltageappliedonCMinexternalreferencemode 1.5±0.05 V
CLOCKINPUT
Fs Inputclocksamplerate 1 125 MSPS
Sinewave,ac-coupled 0.4 3
Inputclockamplitudedifferential LVPECL,ac-coupled 1.6 VPP
(VCLKP–VCLKM) LVDS,ac-coupled 0.7
LVCMOS,single-ended,ac-coupled 3.3 V
Inputclockdutycycle 35% 50% 65%
DIGITALOUTPUTS
Default
ForC ≤5pFandDRVDD≥2.2V
LOAD strength
Outputbufferdrivestrength(1) ForC ≥5pFandDRVDD≥2.2V Maximum
LOAD strength
Maximum
ForDRVDD<2.2V
strength
CMOSinterface 5
Maximumexternalload
C capacitancefromeachoutputpin LVDSinterface,withoutinternaltermination 5 pF
LOAD
toDRGND
LVDSinterface,with100Ωinternaltermination 10
R DifferentialloadresistancebetweentheLVDSoutputpairs(LVDSmode) 100 Ω
LOAD
T Operatingfree-airtemperature –40 85 °C
A
(1) SeetheOutputbufferstrengthprogrammabilityinapplicationsection
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ELECTRICAL CHARACTERISTICS
Typicalvaluesat25°C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=
MIN MAX
3.3V,DRVDD=1.8Vto3.3V,samplingfrequency=125MSPS,50%clockdutycycle,–1dBFSdifferentialanaloginput,
internalreferencemode,appliestoCMOSandLVDSinterfaces(unlessotherwisenoted).
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
Resolution 11 bits
ANALOGINPUTS
Differentialinputvoltagerange 2 V
PP
Differentialinputresistance(atdc) SeeFigure33 >1 MΩ
Differentialinputcapacitance SeeFigure34 7 pF
Analoginputbandwidth 450 MHz
Analoginputcommonmodecurrent(perinputpin) 125 μA
VCMcommonmodevoltageoutput 1.5 V
VCMoutputcurrentcapability 4 mA
POWERSUPPLY
Analogsupplycurrent(AVDD) 216
ISS Outputbuffersupplycurrent(DRVDD) DRVDD=1.8V,2.5MHzinputsignal mA
CMOSinterface noloadcapacitance(1) 17
Totalpower–CMOSinterface 0.74 W
Totalpower–CMOSinterface DRVDD=3.3V,50MHzinputsignal
1.225 W
10pFloadcapacitance
Totalpower–LVDSinterface DRVDD=3.3V 0.94 W
Globalpowerdown 30 60 mW
DCACCURACY
Nomissingcodes Specified
DNL DifferentialNon-Linearity -0.8 ±0.4 0.8 LSB
INL IntegralNon-Linearity -3.5 ±1 3.5 LSB
E OffsetError -10 ±3 10 mV
O
Offseterrortemperaturecoefficient 0.05 mV/°C
Therearetwosourcesofgainerror–internalreferenceinaccuracyandchannelgainerror
Gainerrorduetointernalreferenceinaccuracy
E -1 ±0.25 1 %FS
GREF alone
E Gainerrorofchannelalone(2) -1 ±0.3 1 %FS
GCHAN
Channelgainerrortemperaturecoefficient 0.005 Δ%/°C
(1) InCMOSmode,theDRVDDcurrentscaleswiththesamplingfrequencyandtheloadcapacitanceonoutputpins(seeFigure30).
(2) Thisisspecifiedbydesignandcharacterization;itisnottestedinproduction.
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ELECTRICAL CHARACTERISTICS (continued)
Typicalvaluesat25°C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=
MIN MAX
3.3V,DRVDD=1.8Vto3.3V,samplingfrequency=125MSPS,50%clockdutycycle,–1dBFSdifferentialanaloginput,
internalreferencemode,appliestoCMOSandLVDSinterfaces(unlessotherwisenoted).
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
Fin=10MHz 67.2
Fin=50MHz 65.5 67.1
Fin=70MHz 67.1
SNR Signaltonoiseratio 0dBgain 66.8 dBFS
Fin=170MHz
3.5dBgain 66.4
0dBgain 66.6
Fin=230MHz
3.5dBgain 66.2
Fin=10MHz 67.1
Fin=50MHz 65 66.9
Fin=70MHz 66.9
SINAD Signaltonoiseanddistortionratio 0dBgain 66.5 dBFS
Fin=170MHz
3.5dBgain 66.2
0dBgain 66.3
Fin=230MHz
3.5dBgain 65.9
ENOB Effectivenumberofbits Fin=50MHz 10.5 10.8 LSB
Fin=10MHz 89
Fin=50MHz 75 79
Fin=70MHz 85
SFDR Spuriousfreedynamicrange 0dBgain 82 dBc
Fin=170MHz
3.5dBgain 84
0dBgain 78
Fin=230MHz
3.5dBgain 80
Fin=10MHz 87
Fin=50MHz 72 77
Fin=70MHz 83
THD Totalharmonicdistortion 0dBgain 79 dBc
Fin=170MHz
3.5dBgain 81
0dBgain 75
Fin=230MHz
3.5dBgain 77
Fin=10MHz 95
Fin=50MHz 75 93
Fin=70MHz 93
HD2 Secondharmonicdistortion 0dBgain 85 dBc
Fin=170MHz
3.5dBgain 87
0dBgain 82
Fin=230MHz
3.5dBgain 84
Fin=10MHz 89
Fin=50MHz 75 79
Fin=70MHz 85
HD3 Thirdharmonicdistortion 0dBgain 82 dBc
Fin=170MHz
3.5dBgain 84
0dBgain 78
Fin=230MHz
3.5dBgain 80
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ELECTRICAL CHARACTERISTICS (continued)
Typicalvaluesat25°C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=
MIN MAX
3.3V,DRVDD=1.8Vto3.3V,samplingfrequency=125MSPS,50%clockdutycycle,–1dBFSdifferentialanaloginput,
internalreferencemode,appliestoCMOSandLVDSinterfaces(unlessotherwisenoted).
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
Fin=10MHz 94
Fin=50MHz 92
Worst
Otherthansecond,thirdharmonics Fin=70MHz 94 dBc
Spur
Fin=170MHz 90
Fin=230MHz 88
F1=185MHz,F2=190MHz
IMD 2-Toneintermodulationdistortion 88 dBFS
eachtoneat–7dBFS
Recoverytowithin1%(offinal 1 clock
Inputoverloadrecovery value)for6-dBoverloadwithsine cycles
waveinput
Cross-talk Cross-talksignalfrequencyupto 95 dB
100MHz
For100mVppsignalonAVDD
PSRR ACPowersupplyrejectionratio 45 dBc
supply,frequencyupto10MHz
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DIGITAL CHARACTERISTICS
TheDCspecificationsrefertotheconditionwherethedigitaloutputsarenotswitching,butarepermanentlyatavalidlogic
level0or1.AVDD=3.3V,DRVDD=1.8Vto3.3V,unlessotherwisespecified.
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
DIGITALINPUTS
High-levelinputvoltage 2.4 V
Low-levelinputvoltage 0.8 V
High-levelinputcurrent 33 μA
Low-levelinputcurrent –33 μA
Inputcapacitance 4 Pf
DIGITALOUTPUTS–CMOSMODE,DRVDD=1.8to3.3V
High-leveloutputvoltage DRVDD V
Low-leveloutputvoltage 0 V
Outputcapacitance(internaltodevice) 2 pF
DIGITALOUTPUTS–LVDSMODE(1) (2),DRVDD=3.3V
High-leveloutputvoltage 1375 mV
Low-leveloutputvoltage 1025 mV
|V | Outputdifferentialvoltage 250 350 500 mV
OD
V Outputoffsetvoltage Common-modevoltageofOUTPandOUTM 1200 mV
OS
Outputcapacitanceinsidethedevice,from
OutputCapacitance 2 pF
eitheroutputtoground
(1) LVDSbuffercurrentsetting,I =3.5mA.
O
(2) ExternaldifferentialloadresistancebetweentheLVDSoutputpairs,R =100Ω.
LOAD
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TIMING REQUIREMENTS – LVDS AND CMOS MODES(1)
Typicalvaluesareat25°C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoTMAX=85°C,AVDD
MIN
=3.3V,DRVDD=1.8Vto3.3V,samplingfrequency=125MSPS,sinewaveinputclock,3V clockamplitude,C =5pF
PP LOAD
(2),Io=3.5mA,R =100Ω (3),nointernaltermination,unlessotherwisenoted.
LOAD
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
t Aperturedelay 0.8 1.8 2.8 ns
a
|ta1-ta2|,Channel-to-channelwithinthesamedevice 50
Aperturedelaymatching |ta1-ta2|,Channel-to-channelacrosstwodevicesatsame 450 ps
temperature
t Aperturejitter 130 fsrms
j
fromglobalpowerdown 15 50 μs
Wake-uptime fromchannelstandby 100 200 ns
tovalidoutputdata fromoutputbufferdisable CMOS 100 200 ns
LVDS 200 500 ns
clock
default,afterreset 14
cycles
clock
Latency inlowlatencymode 10
cycles
clock
withdecimationfilterenabled 15
cycles
DDRLVDSMODE(4)DRVDD=3.3V
t Datasetuptime(5) Datavalid (6)tozero-crossingofCLKOUTP 0.6 1.5 ns
su
t Dataholdtime(5) Zero-crossingofCLKOUTPtodatabecominginvalid(6) 1.0 2.3 ns
h
Inputclockrisingedgecross-overtooutputclockrisingedge
t Clockpropagationdelay cross-over 3.5 5.5 7.5 ns
PDI
20MSPS≤Samplingfrequency≤125MSPS
LVDSbitclockduty Dutycycleofdifferentialclock,(CLKOUTP-CLKOUTM)
46% 49% 52%
cycle 10MSPS≤Samplingfrequency≤125MSPS
Risetimemeasuredfrom–100mVto+100mV
t Datarisetime 70 110 170 ps
RISE 1MSPS≤Samplingfrequency≤125MSPS
Falltimemeasuredfrom+100mVto–100mV
t Datafalltime 70 110 170 ps
FALL 1MSPS≤Samplingfrequency≤125MSPS
Risetimemeasuredfrom–100mVto+100mV
t Outputclockrisetime 70 110 170 ps
CLKRISE 1MSPS≤Samplingfrequency≤125MSPS
Falltimemeasuredfrom+100mVto–100mV
t Outputclockfalltime 70 110 170 ps
CLKFALL 1MSPS≤Samplingfrequency≤125MSPS
PARALLELCMOSMODEDRVDD=2.5Vto3.3V
t Datasetuptime(5) Datavalid(7)to50%ofCLKOUTrisingedge 2.0 3.5 ns
su
t Dataholdtime (5) 50%ofCLKOUTrisingedgetodatabecominginvalid(7) 2.0 3.5 ns
h
50%ofinputclockrisingedgeto50%ofCLKOUTrisingedge
t Clockpropagationdelay 5.8 7.3 8.8 ns
PDI 20MSPS≤Samplingfrequency≤125MSPS
Dutycycleofoutputclock,CLKOUT
Outputclockdutycycle 45% 53% 60%
10MSPS≤Samplingfrequency≤125MSPS
Risetimemeasuredfrom20%to80%ofDRVDD
t Datarisetime 0.7 1.5 2.5 ns
RISE 1MSPS≤Samplingfrequency≤125MSPS
Falltimemeasuredfrom80%to20%ofDRVDD
t Datafalltime 0.7 1.5 2.5 ns
FALL 1MSPS≤Samplingfrequency≤125MSPS
Risetimemeasuredfrom20%to80%ofDRVDD
t Outputclockrisetime 0.7 1.5 2.5 ns
CLKRISE 1MSPS≤Samplingfrequency≤125MSPS
(1) Timingparametersareensuredbydesignandcharacterizationandnottestedinproduction.
(2) C istheeffectiveexternalsingle-endedloadcapacitancebetweeneachoutputpinandground
LOAD
(3) I referstotheLVDSbuffercurrentsetting;R isthedifferentialloadresistancebetweentheLVDSoutputpair.
O LOAD
(4) Measurementsaredonewithatransmissionlineof100Ωcharacteristicimpedancebetweenthedeviceandtheload.
(5) Setupandholdtimespecificationstakeintoaccounttheeffectofjitterontheoutputdataandclock.
(6) DatavalidreferstoLOGICHIGHof+100.0mVandLOGICLOWof–100.0mV.
(7) DatavalidreferstoLOGICHIGHof2V(1.7V)andLOGICLOWof0.8V(0.7V)forDRVDD=3.3V(2.5V)
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TIMING REQUIREMENTS – LVDS AND CMOS MODES(1) (continued)
Typicalvaluesareat25°C,minandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoTMAX=85°C,AVDD
MIN
=3.3V,DRVDD=1.8Vto3.3V,samplingfrequency=125MSPS,sinewaveinputclock,3V clockamplitude,C =5pF
PP LOAD
(2),Io=3.5mA,R =100Ω(3),nointernaltermination,unlessotherwisenoted.
LOAD
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
Falltimemeasuredfrom80%to20%ofDRVDD
t Outputclockfalltime 0.7 1.5 2.5 ns
CLKFALL 1MSPS≤Samplingfrequency≤125MSPS
PARALLELCMOSINTERFACE,DRVDD=1.8V,maximumbufferdrivestrength(8)
t Starttime Inputclockrisingedgetodatagettingvalid, (9) (10) 8.5 ns
START
t Widthofvaliddatawindow 3.3 6.0 ns
DV
PARALLELCMOSINTERFACE,DRVDD=1.8V,MULTIPLEXEDMODE,FS=65MSPS,maximumbufferdrive
strength
t Starttime,channelA InputclockfallingedgetochannelAdatagettingvalid, (9) (10) 0.8 2.3 ns
START_CHA
t Datavalid,channelA Widthofvaliddatawindow 5.4 6.4 ns
DV_CHA
t Starttime,channelB InputclockrisingedgetochannelBdatagettingvalid 1.1 2.4 ns
START_CHB
t Datavalid,channelB Widthofvaliddatawindow 5 6 ns
DV_CHB
PARALLELCMOSINTERFACE,DRVDD=1.8V,MULTIPLEXEDMODE,FS=40MSPS,maximumbufferdrive
strength
t Starttime,channelA InputclockfallingedgetochannelAdatagettingvalid, (9) (10) –4.5 –3 ns
START_CHA
t Datavalid,channelA Widthofvaliddatawindow 10.3 11.3 ns
DV_CHA
t Starttime,channelB InputclockrisingedgetochannelBdatagettingvalid –4.1 –2.5 ns
START_CHB
t Datavalid,channelB Widthofvaliddatawindow 9.7 10.7 ns
DV_CHB
(8) ForDRVDD<2.2V,outputclockcannotbeusedfordatacapture.Adelayedversionoftheinputclockcanbeused,thatgivesthe
desiredsetup&holdtimesatthereceivingchip
(9) DatavalidreferstoLOGICHIGHof1.26VandLOGICLOWof0.54VforDRVDD=1.8V.
(10) Measuredfromzero-crossingofinputclockhaving50%dutycycle.
Table2.TimingCharacteristicsatLowerSamplingFrequencies
t DATASETUPTIME,ns t DATAHOLDTIME,ns
su h
SamplingFrequency,MSPS MIN TYP MAX MIN TYP MAX
CMOSINTERFACE,DRVDD=2.5TO3.3V
105 2.8 4.3 2.7 4.2
80 4.3 5.8 4.2 5.7
65 5.7 7.2 5.6 7.1
40 10.5 12 10.3 11.8
20 23 24.5 23 24.5
DDRLVDSINTERFACE,DRVDD=3.3V
105 1 2.3
80 2.4 3.8
65 3.8 5.2 1.0 2.3
40 8.5 10
20 21 22.5
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