dsp implementation of a digital non-linear interval control algorithm for a quasi-keyhole plasma arc

239 Pages·2017·11.15 MB·English

by  Matthew Wayne Everett

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2004
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Matthew Wayne Everett
University of Kentucky, [email protected]
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Everett, Matthew Wayne, "DSP IMPLEMENTATION OF A DIGITAL NON-LINEAR INTERVAL CONTROL
ALGORITHM FOR A QUASI-KEYHOLE PLASMA ARC WELDING PROCESS" (2004). University of Kentucky
Master's Theses. 245.
https://uknowledge.uky.edu/gradschool_theses/245
This Thesis is brought to you for free and open access by the Graduate School at UKnowledge. It has been
accepted for inclusion in University of Kentucky Master's Theses by an authorized administrator of UKnowledge.
For more information, please contact [email protected].
ABSTRACT OF THESIS

DSP IMPLEMENTATION OF A DIGITAL NON-LINEAR INTERVAL
CONTROL ALGORITHM FOR A QUASI-KEYHOLE PLASMA ARC
WELDING PROCESS

The Quasi-Keyhole plasma arc welding (PAW) process is a relatively simple concept,
which provides a basis for controlling the weld quality of a subject work piece by cycling the arc
current between a static base and variable peak level. Since the weld quality is directly related to
the degree of penetration and amount of heat that is generated and maintained in the system, the
Non-Linear Interval Control Algorithm provides a methodology for maintaining these
parameters within acceptable limits by controlling the arc current based upon measured peak
current times. The Texas Instrument’s TMS320VC5416 DSK working in conjunction with
Signalware’s AED-109 Data Converter provides a hardware solution to implement this control
algorithm. This study outlines this configuration process and demonstrates its validity.

KEYWORDS: TMS320VC5416 DSK, AED-109, Interval Control, Quasi-Keyhole, Plasma Arc
Welding

Author: Matthew Wayne Everett

Date: 29 May 2004
Copyright 2004, Ma tthew Wayne Everett
DSP IMPLEMENTATION OF A DIGITAL NON-LINEAR INTERVAL
CONTROL ALGORITHM FOR A QUASI-KEYHOLE PLASMA ARC
WELDING PROCESS

By

Matthew Wayne Everett

Dr. YuMing Zhang

Director of Thesis

Dr. William T. Smith

Director of Graduate Studies

Date: 29 May 2004
RULES FOR THE USE OF THE THESES

Unpublished theses submitted for the Master’s degree and deposited in the
University of Kentucky Library are as a rule open for inspection, but are to be used
only with due regard to the rights of the authors. Bibliographical references may
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permission of the author, and with the usual scholarly acknowledgments.

Extensive copying or publication of the thesis in whole or in part also requires the
consent of the Dean of the Graduate School of the University of Kentucky.
THESIS

Matthew Wayne Everett

The Graduate School

University of Kentucky

2004
DSP IMPLEMENTATION OF A DIGITAL NON-LINEAR INTERVAL
CONTROL ALGORITHM FOR A QUASI-KEYHOLE PLASMA ARC
WELDING PROCESS

_______________________________

THESIS
_______________________________

A thesis submitted in partial fulfillment of the
requirements for the degree of Master of Science in Electrical Engineering in the
College of Engineering
at the University of Kentucky

By

Matthew Everett, PE, LSIT, MCP

Lexington, Kentucky

Director: Dr. YuMing Zhang, Department of Electrical and Computer Engineering

Lexington, Kentucky

2004
Copyright 2004, Ma tthew Wayne Everett

At this time, I wish to dedicate this thesis to my mother, Linda Glass. She has always
been an example of principle, perseverance, and dedication. I can only hope that she is proud of
me as I am of her. I love you Mom.
Acknowledgements

This work has been supported and partially funded by the National Science Foundation
under Grant DMI-0114982 and the Center for Manufacturing Systems at the University of
Kentucky.

At this time, I would like to thank Dr. Yuming Zhang for the personal, academic, and
material support he has provided throughout my undergraduate and graduate work at the
University of Kentucky in the Department of Electrical and Computer Engineering. As the
Director of the Welding Research Laboratory and the Applied Sensing and Control Laboratory,
Dr. Zhang has graciously allowed me to participate in this program, utilize his laboratory
facilities, and provide technical guidance. Since first meeting Dr. Zhang in the summer of 2001,
I have found him to not only be extremely intellectually gifted, but also a refreshing individual. I
cannot remember a time when Dr. Zhang was unable to smile and provide an upbeat tone to our
discussions, or in my observations, his discussions with others. The University of Kentucky is
quite fortunate to have a professor such as Dr. Zhang on staff.

I would also like to thank Wei Lu for his technical guidance and patience. Wei is
currently pursuing his PHD here at the University of Kentucky, which I am sure he will complete
quite soon. Wei is a fine individual who enriches the academic community. If in the future our
paths do not cross, I wish Wei and his family the best life has to offer. I will not forget his
gratitude.

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Table of Contents

Acknowledgments …………………………………………………………………….…... iii

List of Tables ……………….………………………………………………………….…. ix

List of Figures ………………..………………………….…………………………….….. x

List of Files …………………..………………………….…………………………….….. xii

1 Introduction
1.1 Objective ……………………………….…………………………………..… 1
1.2 Micro-Processor ……………………………….…………………………..… 1
1.3 Micro-Controller ……………………………………….…………………..… 1
1.4 Digital Signal Processor ……………………………………….…………..… 2
1.5 Daughter Card ……………………………………………………….…..… 2

2 Quasi-Keyhole Plasma Arc Welding Process
2.1 Arc Welding …………………………………………………………...… 4
2.2 Plasma Arc Welding Process and Laboratory Experimental System ….…. 5

3 Digital Signal Processor
3.1 TMS320VC5416 DSP Developmental Starter Kit (DSK) ……………………... 7
3.1.1 DSK Architecture ..………………………….……………………….... 8
3.1.1.1 Emulation …………………………………….…………….…. 8
3.1.1.2 Hardware Expansion …………………………….….……. 8
3.1.1.3 Memory ..……………………………………….…………… 10
3.1.1.3.1 Processor Mode Status Register …………..…. 10
3.1.1.3.2 Program Memory Map for Page 0 and ………..…… 12
Data Memory Map
3.1.1.3.3 Extended Program Memory Map ………….….. 13
3.1.1.3.4 I/O Memory Map …………………………..…. 14
3.1.1.3.5 Data Memory Page Map ………………...….... 14
3.1.1.3.6 Program Memory Page Map …………………...… 15
3.1.1.3.7 Memory Resources ..………………….……….... 16
3.1.1.3.8 Wait State Generator ………………………..…..... 16
3.1.1.4 CPLD Registers ..……………………………………………. 16
3.1.1.4.1 USER_REG Register ..……………………………. 17
3.1.1.4.2 DC_REG Register ………..…………………..... 17
3.1.1.4.3 CODEC_L_CMD and CODEC_H_CMD ………….. 18
Registers

3.1.1.4.4 VERSION Register ………..…………………..... 18
3.1.1.4.5 MISC Register ..……………………………………. 18
3.1.1.4.6 CODEC_CLK Register ..……………………………. 19
3.2 TMS320VC5416 DSP (C5416 DSP) Functional Overview ………..….… 20
3.2.1 5416 Processor ..……………………………………………………. 21
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