Distributed clocking for synchronous SoCs

226 Pages·2017·11.23 MB·English

by  Eldar Zianbetov

Distributed clocking for synchronous SoCs
Eldar Zianbetov
To cite this version:
Eldar Zianbetov. Distributed clocking for synchronous SoCs. Micro and nanotechnolo-
gies/Microelectronics. Université Pierre et Marie Curie - Paris VI, 2013. English. ￿NNT: ￿. ￿tel-
01053729￿
HAL Id: tel-01053729
https://theses.hal.science/tel-01053729
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`
THESE DE DOCTORAT DE
´
l’UNIVERSITE PIERRE ET MARIE CURIE
´ ´
Ecole Doctorale Informatique, Te´le´communications et Electronique
(EDITE)
Pre´sente´e par :
Eldar ZIANBETOV
Pour obtenir le grade de :
´
DOCTEUR de l’UNIVERSITE PIERRE ET MARIE CURIE
Sujet de la the`se :
´
HORLOGERIE DISTRIBUEE POUR LES SOCs SYNCHRONES
Pre´sente´ele:
25.03.2013
Lejuryestcompose´ de:
M.Jean-BaptisteBEGUERET IMSBordeaux Rapporteur
M.DavidNAIRN Universite´ deWaterloo Rapporteur
M.Jean-PierreSCHOELLKOPF SiLiCieL Rapporteur
M.BernardCOURTOIS CNRS Examinateur
M.AlainGREINER UPMC,LIP6 Examinateur
M.ValeriySITNIKOV OdessaStatePolytechnicUniversity Examinateur
M.Franc¸oisANCEAU CNAM DirecteurdeThe`se
M.DimitriGALAYKO UPMC,LIP6 Co-directeurdeThe`se
M.E´ricCOLINET CEA-LETI,Minatec Invite´
M.Je´roˆmeJUILLARD Supe´lec Invite´

DOCTORAL DISSERTATION
PIERRE AND MARIE CURIE UNIVERSITY
Doctoral School of Informatics, Telecommunications and Electronics
(EDITE)
Presented by:
Eldar ZIANBETOV
To obtain the degree of :
DOCTOR OF PHILOSOPHY AT UNIVERSITY OF PIERRE AND
MARIE CURIE
Thesis title :
DISTRIBUTED CLOCKING FOR SYNCHRONOUS SOC
Presentedon:
25.03.2013
Membersofjury:
M.Jean-BaptisteBEGUERET IMSBordeaux Reviewer
M.DavidNAIRN UniversityofWaterloo Reviewer
M.Jean-PierreSCHOELLKOPF SiLiCieL Reviewer
M.BernardCOURTOIS CNRS Examinator
M.AlainGREINER UPMC,LIP6 Examinator
M.ValeriySITNIKOV OdessaStatePolytechnicUniversity Examinator
M.Franc¸oisANCEAU CNAM Supervisor
M.DimitriGALAYKO UPMC,LIP6 Co-Supervisor
M.E´ricCOLINET CEA-LETI,Minatec Invited
M.Je´roˆmeJUILLARD Supe´lec Invited

Abstract
ThisdissertationaddressestheproblemofglobalsynchronizationofcomplexSoCinthe
contextofdeeplysubmicronCMOStechnologies.
Nowadays, to circumvent the difficulties associated with conventional clock distribution
techniques(e.g. tree,mesh)insynchronoussystems,thedesignerswishingtogoonwiththe
GloballySynchronousparadigmareturningtowardclockingtechniquesbreakingawayfrom
conventional approaches (e.g. distributed oscillators, stationary waves, coupled oscillators,
programmabledelays). Thisstudyissituatedonthisresearchaxis.
In this research we studied and elaborated a global distributed clocking system for a
highly reliable synchronous circuit. This clocking scheme is based on a network of oscilla-
tors coupled in phase. Inside each synchronous clocking domain, there is one oscillator that
generates the local clock. To synchronize the oscillators (i.e. domains), each one of them
is controlled by an All-Digital Phase Locked Loop (ADPLL), realizing a phase coupling
betweentheoscillatorsofneighboringzones.
Duringthisresearchwehavedevelopedthespecificationsandselectedanarchitectureof
the network. A theoretical model of the system has been established in a collaboration with
CEA-LETI and Supe´lec laboratories in the framework of ANR HODISS project. We have
analyzed the behavior of the system in simulations on different abstraction levels, investi-
gatedthestabilityconditionsofitssynchronousoperation.
An All-Digital Phase Locked Loop (ADPLL) has been proposed for the role of an el-
ementary node of distributed clocking network. The use of ADPLL permits to circumvent
difficulties of implementation, which are usually associated with analog PLL. We have de-
signed the main blocks of the ADPLL: a Digitally-Controlled Oscillator (DCO), a Phase-
FrequencyDetector(PFD)andanerrorprocessingblock. Acell-baseddesigntechniquehas
been adapted for the design of DCO layout. This technique significantly reduced the com-
plexity of the oscillator’s implementation. The remaining blocks have been designed in a
commondigitaldesignflow.
In order to reduce the risks associated with silicon implementation, the system has been
validated in a FPGA prototyping platform. The results of the measurements showed that
clockingnetworkbehavesaspredictedbythetheoryandsimulations.
Two prototype circuits have been designed, implemented and tested in a 65 nm STMi-
croelectronics CMOS technology. The first one is a proof of concept of a designed highly
linear and monotonous DCO. The measured parameters of oscillator showed the compli-
ance with specifications. The measured performance demonstrated the <15 ps rms jitter,
while consuming 6.2 mW/GHz with 1.1 V supply voltage. The tuning range of the oscil-
lator is 999-2480 MHz under 10 bit resolution. The second chip is a 4×4 node clocking
networkwhichconsistsof16distributedADPLLs. Eachofthememploysadesignedearlier
DCO, PFD and error processing block. The experiments showed that proposed technique of
distributedclockgenerationisfeasibleinarealCMOSchipenvironment. Themeasuredper-
formance demonstrated the timing error between neighbor oscillators less than 60 ps, while
powerconsumptionis98.47mW/GHz.
Thesistitle: DistributedclockingforsynchronousSoC
Key words: synchronous clocking, multioscillator architecture, all-digital phase locked
loop,digitally-controlledoscillator,bang-bangdetector,time-to-digitalconverter
Thesis Supervisor: Franc¸ois ANCEAU, Professor at Conservatoire national des arts et
me´tiers
Thesis Co-Supervisor: Dimitri GALAYKO, Associate Professor at Pierre and Marie
CurieUniversity(ParisVI)
InMemoryOfMyMother,WhoPassedAwayIn1994

The meaning of this degree is that the recipient of instruction is examined for the last
timeinhislife,andispronouncedcompletelyfull.
StephenLeacock. McGillUniversity,1912.