Digitally Calibrated Analog-to-Digital Converters in Deep Sub-micron CMOS

188 Pages·2008·5.2 MB·English

Digitally Calibrated Analog-to-Digital Converters in
Deep Sub-micron CMOS
Cheongyuen (Bill) Tsang
Electrical Engineering and Computer Sciences
University of California at Berkeley
Technical Report No. UCB/EECS-2008-67
http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-67.html
May 22, 2008
Copyright © 2008, by the author(s).
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Digitally Calibrated Analog-to-Digital Converters in Deep Sub-micron
CMOS
by
Cheongyuen William Tsang
B.S. (University of Michigan, Ann Arbor) 2000
M.S. (University of California, Berkeley) 2003
A dissertation submitted in partial satisfaction of the
requirements for the degree of
Doctor of Philosophy
in
Engineering - Electrical Engineering and Computer Sciences
in the
GRADUATE DIVISION
of the
UNIVERSITY OF CALIFORNIA, BERKELEY
Committee in charge:
Professor Borivoje Nikolic´, Chair
Professor Robert Brodersen
Professor Paul Wright
Spring 2008
The dissertation of Cheongyuen William Tsang is approved:
Chair Date
Date
Date
University of California, Berkeley
Spring 2008
Digitally Calibrated Analog-to-Digital Converters in Deep Sub-micron
CMOS
Copyright 2008
by
Cheongyuen William Tsang
1
Abstract
Digitally Calibrated Analog-to-Digital Converters in Deep Sub-micron CMOS
by
Cheongyuen William Tsang
Doctor of Philosophy in Engineering - Electrical Engineering and Computer Sciences
University of California, Berkeley
Professor Borivoje Nikolic´, Chair
We present and implement an adaptive digital technique to calibrate pipelined analog-to-
digital converters (ADCs). Rather than achieving linearity by adjustment of analog compo-
nent values, the new approach infers component errors from conversion results and applies
digital postprocessing to correct those results. The scheme proposed here draws close anal-
ogy to the channel equalization problem commonly encountered in digital communications.
We show that, with the help of a slow but accurate ADC, the proposed code-domain adap-
tive digital filter is sufficient to remove the effects of component errors including capacitor
mismatch,signal-dependentfiniteop-ampgain,op-ampoffset,andsampling-switch-induced
offset. The algorithm is all digital, fully adaptive, data-driven, and operates in the back-
ground. StrongtradeoffsbetweenaccuracyandspeedofpipelinedADCsaregreatlyrelaxed
inthisapproachwiththeaidofdigitalcorrectiontechniques. Analogprecisionproblemsare
translatedintothecomplexityofdigitalsignal-processingcircuits, allowingthisapproachto
2
benefit from CMOS device scaling in contrast to most conventional correction techniques.
To demonstrate the idea, a prototype has been designed and fabricated in 0.13µm
with1.35Vpowersupply. ThesystemmainlyconsistsofapipelinedADC,areferenceADC,
and an adaptive digital filter in FPGA. The measured results show that the SNR improves
from 28.1dB before calibration to 59.4dB after calibration at 100MS/s with a 411kHz. The
SFDRimprovesfrom29.8dBto67.8dB.Thetotalpowerconsumptionofthechipis448mW
and the estimated power consumption of the adaptive digital filter is 7mW at 100MHz.
Professor Borivoje Nikolic´
Dissertation Committee Chair
i
To my parents
ii
Contents
List of Figures vi
List of Tables x
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 State-of-the-Art Calibrated ADCs . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Fully Digital Background Calibration of Pipelined ADCs 5
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Overview of Pipelined ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Review of ADC Calibration Techniques . . . . . . . . . . . . . . . . . . . . 7
2.4 Least-Mean-Square (LMS) Equalization Method . . . . . . . . . . . . . . . 12
2.5 Code-Domain Filtering Approach . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5.1 Code-Domain Formulation of 1.5-b/Stage Pipelined ADC Architecture 13
2.5.2 Code-Domain Formulation of 2.5-b/Stage Pipelined ADC Architecture 14
2.5.3 Code-Domain Formulation of Residue Amplifier with Nonlinear Am-
plifier Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.5.4 Code-Domain Formulation of a Complete Pipelined ADC . . . . . . 18
2.5.5 Code-Domain Filtering Technique System Architecture . . . . . . . 21
2.6 Behavioral Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.6.1 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.6.2 Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3 High-Accuracy Reference ADC 32
3.1 Background Calibrated Analog-to-Digital Converter (ADC) System Overview 32
3.2 Slow-but-Accurate A/D Converters . . . . . . . . . . . . . . . . . . . . . . . 33
3.3 Integrating A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.4 Successive Approximation A/D Converters . . . . . . . . . . . . . . . . . . 35
3.5 Algorithmic/Cyclic A/D Converters . . . . . . . . . . . . . . . . . . . . . . 36
iii
3.6 Oversampling A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.7 First-Order Sigma-Delta (Σ∆) A/D Converters . . . . . . . . . . . . . . . . 38
3.8 Second-Order Σ∆ A/D Converters . . . . . . . . . . . . . . . . . . . . . . . 39
3.9 Multi-Stage Noise Shaping (MASH) Σ∆ A/D Converters . . . . . . . . . . 40
3.9.1 2-1 MASH Σ∆ A/D Converters . . . . . . . . . . . . . . . . . . . . . 40
3.10 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4 Design of Σ∆ A/D Converter 44
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.2 Σ∆ ADC as a DC Voltmeter . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.3 Reference ADC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3.1 Second-Order Σ∆ Architecture . . . . . . . . . . . . . . . . . . . . . 46
4.3.2 2-1 MASH Σ∆ Architecture . . . . . . . . . . . . . . . . . . . . . . . 47
4.4 Simulink Models of Σ∆ ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.4.1 Dynamic Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.4.2 DC Tones and Dithering . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.4.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.4.4 Settling of Finite Impulse Response (FIR) Decimation Filter . . . . 53
4.5 Integrator Signal Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.6 Thermal Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.7 Flicker Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.8 Effects of Circuit Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.9 Matching of λ, β in 2-1 MASH Σ∆ ADCs . . . . . . . . . . . . . . . . . . . 64
4.10 Amplifier DC Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.11 Amplifier Settling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.12 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5 Circuit Implementation of Σ∆ A/D Converter Prototype 69
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.2 Switched-Capacitor Integrators . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.2.1 First Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.2.2 Second Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.2.3 Third Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.3 Operational Trans-conductance Amplifiers (OTAs) . . . . . . . . . . . . . . 76
5.3.1 Main OTAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.3.2 N-side Boosters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.3.3 P-side Boosters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3.4 Switched-Capacitor Common-Mode Feedback (CMFB) Circuits . . . 82
5.4 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.5 Latches and DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.6 Sampling Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.7 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92