Digitally assisted pipeline ADCs : theory and implementation

176 Pages·1994·6.59 MB·English

by  Boris Murmann

DIGITALLY ASSISTED PIPELINE ADCs
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Digitally Assisted Pipeline
ADCs
Theory and Implementation
by
Boris Murmann
Standford University
and
Bernhard E. Boser
University of California, Berkeley
KLUWER ACADEMIC PUBLISHERS
NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW
eBook ISBN: 1-4020-7840-4
Print ISBN: 1-4020-7839-0
©2004 Kluwer Academic Publishers
New York, Boston, Dordrecht, London, Moscow
Print ©2004 Kluwer Academic Publishers
Dordrecht
All rights reserved
No part of this eBook may be reproduced or transmitted in any form or by any means, electronic,
mechanical, recording, or otherwise, without written consent from the Publisher
Created in the United States of America
Visit Kluwer Online at: http://kluweronline.com
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Dedication
To our families.
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Contents
List of Figures xi

List of Tables xv

Acknowledgments xvii

Preface xix

1. INTRODUCTION 1

1. Motivation 1

2. Overview 2

3. Chapter Organization 4

2. PERFORMANCE TRENDS 5

1. Introduction 5

2. Digital Performance Trends 6

3. ADC Performance Trends 7

3. SCALING ANALYSIS 15

1. Introduction 15

2. Basic Device Scaling from a Digital Perspective 16

3. Technology Metrics for Analog Circuits 17

4. Scaling Impact on Matching-Limited Circuits 25

5. Scaling Impact on Noise-Limited Circuits 33

4. IMPROVING ANALOG CIRCUIT EFFICIENCY 43

1. Introduction 43

2. Analog Circuit Challenges 43

3. The Cost of Feedback 45
viii Digitally Assisted Pipeline ADCs
4. Two-Stage Feedback Amplifier vs. Open-Loop Gain Stage 46

5. Discussion 52

5. OPEN-LOOP PIPELINED ADCS 53

1. A Brief Review of Pipelined ADCs 53

2. Conventional Stage Implementation 54

3. Open-Loop Pipeline Stages 55

4. Alternative Transconductor Implementations 60

6. DIGITAL NONLINEARITY CORRECTION 63

1. Overview 63

2. Error Model and Digital Correction 65

3. Alternative Error Models 74

7. STATISTICS-BASED PARAMETER ESTIMATION 75

1. Introduction 75

2. Modulation Approach 76

3. Required Sub-ADC and Sub-DAC Redundancy 77

4. Parameter Estimation Based on Residue Differences 79

5. Statistics Based Difference Estimation 84

6. Complete Estimation Block 87

7. Simulation Example 90

8. Discussion 97

8. PROTOTYPE IMPLEMENTATION 101

1. ADC Architecture 101

2. Stage 1 102

3. Stage 2 106

4. Post-Processor 107

9. EXPERIMENTAL RESULTS 109

1. Layout and Packaging 109

2. Test Setup 111

3. Measured Results 112

4. Post-Processor Complexity 121

10. CONCLUSION 123

1. Summary 123

2. Suggestions for Future Work 124

Appendices

A- Open-Loop Charge Redistribution 127

B- Estimator Variance 131
Contents ix

C- LMS Loop Analysis 137

1. Time Constant 137

2. Output Variance 138

3. Maximum Gain Parameters 139

References 143

Index 153