Digital Phase Locked Loops for Radio Frequency Synthesis Mahmoud, Ahmed

179 Pages·2017·8.55 MB·English

Digital Phase Locked Loops for Radio Frequency Synthesis
Mahmoud, Ahmed
2017
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Mahmoud, A. (2017). Digital Phase Locked Loops for Radio Frequency Synthesis. [Doctoral Thesis
(monograph), Department of Electrical and Information Technology]. Department of Electrical and Information
Technology, Lund University.
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1
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LUND UNIVERSITY
PO Box 117
221 00 Lund
[phone]
Digital Phase Locked
Loops for Radio
Frequency Synthesis
Ahmed Mahmoud
DoctoralThesis
ElectricalEngineering
Lund,December2017
AhmedMahmoud
DepartmentofElectricalandInformationTechnology
ElectricalEngineering
LundUniversity
P.O.Box118,22100Lund,Sweden
Seriesoflicentiateanddoctoraltheses
ISSN1654-790X;No.106
ISBN978-91-7753-419-8(print)
ISBN978-91-7753-420-4(pdf)
'2017AhmedMahmoud
TypesetinPalatinoandHelveticausingLATEX2ε.
PrintedinSwedenbyTryckerietiE-huset,LundUniversity,Lund.
Nopartofthisthesismaybereproducedortransmittedinanyformorbyany
means, electronically or mechanical, including photocopy, recording, or any
informationstorageandretrievalsystem,withoutwrittenpermissionfromthe
author.
Popular Science
The demand of handsets with high data rate capability, more complex fea-
turesandlongbatterylifeatanaffordablecosthasbeenthedrivingforcebe-
hindmostinnovationsinwirelesscommunicationsystemsforconsumerelec-
tronics. These innovations have made radio communication smooth and effi-
cient,therebymaximizingitsimpactworldwideandreshapingthewaydatais
sharedbetweenpeople.
Central to wireless communication systems are the radio transmitter and
receiver, which are responsible for transmitting and receiving data between
wirelessdevices.Akeyfunctioninbothisfrequencygeneration,whichisneeded
toplacethetransmitteddatainaverywellcontrolledregionofthefrequency
spectrum (typically, at radio-frequency, RF), and, conversely, to transfer the
received data from RF to the original low frequency. Frequency generation
is usually accomplished by means of a phase-locked loop (PLL), where, start-
ingfromaverystablereferencefrequencyofafewtensofMHz, veryprecise
frequenciesuptoseveralGHzaresynthesized.
The wireless communication environment is very hostile, with many inter-
ference sources potentially able to contaminate the often tiny desired signal.
ThisposestoughrequirementsonthepurityoftheRFsignalgeneratedbythe
PLL,sincethePLLmustcoexistwithanumberofotherradioblocksintegrated
onthesamesilicondie. Inparticular,theeverlargerdigitalsignalprocessing
units in the typical radio fabricated in a modern CMOS process generate a
largeamountofswitchingnoise,causedbyallcommutationsbetweenlogic0
andlogic1occurringthere,whichmayeasilyaffecttheintegrityofthePLL.
At the same time, the conventional circuit design of analog functions, of
whichthePLLisanexample, isbecomingincreasinglyproblematic, asultra-
scaledCMOStechnologiesmandatetheuseofverylowpowersupplyvoltages,
as a consequence of the extremely reduced dimensions of the CMOS devices.
iii
Furthermore, the effort associated to bring about such a technology scaling
hasturnedoncecheapCMOSprocessesintoveryexpensiveones,andtherel-
ativelylargeareaoccupiedbyanalogcircuitsisweighingheavilyonthetotal
costoftheradiotransceiver.
Because of the above reasons, we are witnessing an unrelenting migration
ofanalogfunctionstowardsthedigitaldomain, andtheforemostexampleof
this is the digital PLL, which can exploit all the advantages, in terms of pro-
grammability,reconfigurability,adaptivity,andcompactness,thatarebeyond
thereachofthetraditionalPLL
In this dissertation, several techniques are demonstrated, that improve the
designofthedigitalPLL,intermsofbothoverallarchitectureandindividual
PLLsub-blocks,obtainingexcellentperformances.
iv
Contents
PopularScience iii
Preface ix
Acknowledgments xi
ListofAbbreviations xiii
ListofFigures xvii
ListofTables xxiii
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 ResearchContribution . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 ThesisOutline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 FrequencySynthesizerOverview 7
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 FrequencySynthesizersinTransceivers . . . . . . . . . . . . . . 8
2.2.1 SuperheterodyneTransceiver . . . . . . . . . . . . . . . . . 9
2.2.2 HomodyneTransceiver . . . . . . . . . . . . . . . . . . . . 10
2.3 FrequencySynthesizerArchitectures . . . . . . . . . . . . . . . . 11
2.3.1 DirectAnalogFrequencySynthesizer . . . . . . . . . . . . 11
2.3.2 DirectDigitalFrequencySynthesizer . . . . . . . . . . . . 12
v
2.3.3 IndirectFrequencySynthesizer . . . . . . . . . . . . . . . . 13
2.3.4 HybridFrequencySynthesizer . . . . . . . . . . . . . . . . 15
2.4 PerformanceMetricsofTheFrequencySynthesizer . . . . . . . 15
2.4.1 FrequencyTuningRangeandFrequencyResolution . . . . 16
2.4.2 SpectralPurity . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.2.1 PhaseNoise . . . . . . . . . . . . . . . . . . . . 16
2.4.2.2 SpuriousTones . . . . . . . . . . . . . . . . . . 20
2.4.3 SwitchingTime . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4.4 PowerConsumption,SizeandPortability . . . . . . . . . . 22
3 DPLLFundamentals 23
3.1 DPLLArchitectures . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 TDC-BasedDPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.1 DiscreteandContinuous-TimeModels . . . . . . . . . . . 25
3.2.1.1 DigitallyControlledOscillator . . . . . . . . . 25
3.2.1.2 TimetoDigitalConverter. . . . . . . . . . . . 27
3.2.1.3 DigitalLoopFilter . . . . . . . . . . . . . . . . 28
3.2.1.4 MMDand∆ΣModulator . . . . . . . . . . . . 29
3.2.1.5 OverallTransferFunctions . . . . . . . . . . . 31
3.2.2 NoiseSourcesAnalysis . . . . . . . . . . . . . . . . . . . . 34
3.2.2.1 ReferenceNoiseTransferFunction. . . . . . . 34
3.2.2.2 TDCNoiseTransferFunction . . . . . . . . . 35
3.2.2.3 DCONoiseTransferFunction . . . . . . . . . 36
3.2.2.4 ∆ΣModulatorNoiseTransferFunction . . . . 37
3.2.3 PhaseNoisePerformance . . . . . . . . . . . . . . . . . . . 38
3.3 Bang-Bang-BasedDPLL . . . . . . . . . . . . . . . . . . . . . . . 40
3.3.1 DiscreteandContinuous-TimeModels . . . . . . . . . . . 42
3.3.1.1 DTCControl . . . . . . . . . . . . . . . . . . . 48
3.3.1.2 Pre-distorter . . . . . . . . . . . . . . . . . . . 50
3.3.1.3 LoopBandwidthRegulation . . . . . . . . . . 54
3.3.1.4 FrequencyAcquisitionController . . . . . . . 55
4 DigitallyControlledOscillator 57
4.1 OscillatorFundamentals . . . . . . . . . . . . . . . . . . . . . . . 58
4.2 LC-TankOscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.1 PrinciplesofLC-TankOscillator . . . . . . . . . . . . . . . 59
4.2.2 Cross-CoupledDifferentialPair . . . . . . . . . . . . . . . 60
4.3 ReviewofExistingPhaseNoiseModels . . . . . . . . . . . . . . 61
vi
4.3.1 HajimiriandLee’sPhaseNoiseModel . . . . . . . . . . . . 62
4.3.2 PepeandAndreani’sPhaseNoiseModel . . . . . . . . . . 63
4.4 OscillatorPerformanceParameters . . . . . . . . . . . . . . . . . 64
4.5 FrequencyTuningOverview. . . . . . . . . . . . . . . . . . . . . 65
4.5.1 WideFrequencyTuningRangeTechniques . . . . . . . . . 67
4.5.1.1 Dual-CoreDCO . . . . . . . . . . . . . . . . . 67
4.5.1.2 Transformer-BasedDCO . . . . . . . . . . . . 68
4.5.1.3 SwitchedInductorsDCO . . . . . . . . . . . . 70
4.5.1.4 Mode-SwitchingDCO . . . . . . . . . . . . . . 72
4.5.2 FineTuningTechniques . . . . . . . . . . . . . . . . . . . . 73
4.5.2.1 ∆ΣModulatorDithering . . . . . . . . . . . . 74
4.5.2.2 CapacitiveDividerTechnique . . . . . . . . . 76
4.5.2.3 CapacitiveDegenerationMethod . . . . . . . 77
4.5.2.4 MOSVaractorsTechniques . . . . . . . . . . . 78
4.6 OscillatorPulling . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.6.1 EMSimulationSetup . . . . . . . . . . . . . . . . . . . . . 80
4.6.2 EMSimulationResults . . . . . . . . . . . . . . . . . . . . 84
5 TDCandDTC 89
5.1 TDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.1.1 PerformanceParameters . . . . . . . . . . . . . . . . . . . . 91
5.1.1.1 Resolution . . . . . . . . . . . . . . . . . . . . 91
5.1.1.2 DynamicRange . . . . . . . . . . . . . . . . . 91
5.1.1.3 LinearandNon-LinearNon-Idealities. . . . . 92
5.1.1.4 DeadTime,ConversionTimeandLatency . . 93
5.1.2 TDCArchitecturesReview . . . . . . . . . . . . . . . . . . 94
5.1.2.1 Delay-LineTDC . . . . . . . . . . . . . . . . . 94
5.1.2.2 VernierTDC . . . . . . . . . . . . . . . . . . . 95
5.1.2.3 GRO-TDC. . . . . . . . . . . . . . . . . . . . . 97
5.1.2.4 2DVernierTDC . . . . . . . . . . . . . . . . . 99
5.1.2.5 2DGVTDC . . . . . . . . . . . . . . . . . . . . 101
5.1.2.6 Time-Amplifier-BasedTDC . . . . . . . . . . . 102
5.2 DTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.2.1 DTCArchitecturesReview . . . . . . . . . . . . . . . . . . 104
5.2.1.1 Shunt-CapacitorInverter-BasedDTC . . . . . 104
5.2.1.2 Current-StarvedInverter-BasedDTC . . . . . 105
5.2.1.3 Voltage-Comparator-BasedDTC . . . . . . . . 105
5.2.1.4 PhaseInterpolation-BasedDTC . . . . . . . . 107
vii
6 ExperimentalResults 109
6.1 A2.8-to-5.8GHzHarmonicVCOBasedonan8-shapedInduc-
torina28nmUTBBFD-SOICMOSProcess . . . . . . . . . . . 109
6.1.1 VCOPrototype . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.1.2 MeasurementResults . . . . . . . . . . . . . . . . . . . . . 115
6.2 AWideBandFractional-NDPLLwithaNoiseShaping2DTDC
forLTE-AApplications. . . . . . . . . . . . . . . . . . . . . . . . 116
6.2.1 LMSBasedQuantizationNoiseCancellation . . . . . . . . 117
6.2.2 Subblocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.2.2.1 Class-DDCO . . . . . . . . . . . . . . . . . . . 121
6.2.2.2 DividerandMASH1-1-1∆ΣModulator . . . 123
6.2.2.3 DigitalLoopFilter . . . . . . . . . . . . . . . . 125
6.2.3 SimulationResults . . . . . . . . . . . . . . . . . . . . . . . 126
6.3 A2.8-3.8GHzLow-SpurDTC-BasedDPLLwithaClass-DDCO
in65nmCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3.1 CircuitImplementation . . . . . . . . . . . . . . . . . . . . 129
6.3.1.1 DTCandFractionalFrequencyDivider . . . . 129
6.3.1.2 DTCLinearization . . . . . . . . . . . . . . . . 131
6.3.2 MeasurementResults . . . . . . . . . . . . . . . . . . . . . 132
7 Conclusions 137
Bibliography 141
viii
Preface
This thesis summarizes my academic work carried out in the mixed-signal
groupatthedepartmentofElectricalandInformationTechnology,LundUni-
versity,Sweden,fromNovember2012toAugust2017. Inthefollowing,Iwill
describemycontributionstothepublishedpapersIhaveco-authored.
I L. Fanori, A. Mahmoud, T. Mattsson, P. Caputa, S. Ramo, and P. An-
dreani,"A2.8-to-5.8GHzharmonicVCOina28nmUTBBFD-SOICMOS
process," in Radio Frequency Integrated Circuits Symposium (RFIC),
2015IEEE,2015,pp. 195-198.
Contributions. I helped the first author with circuit simulations and
measurementsonthedesignedoscillator.
II A.Mahmoud,L.Fanori,T.Mattsson,P.Caputa,andP.Andreani,"A2.8-
to-5.8 GHz harmonic VCO based on an 8-shaped inductor in a 28 nm
UTBB FD-SOI CMOS process," Analog Integrated Circuits and Signal
Processing,vol. 88,no. 3,pp. 391-399,2016.
Contributions. I performed all of the analysis and simulations of the
magnetic coupling of the 8-shaped inductor. I helped the first author
withcircuitsimulationsandmeasurementsonthedesignedoscillator. I
wrotethesectionaboutthemagneticcoupling,andre-wrotetherest.
III A.Mahmoud, P. Andreani, and P. Lu, "A 65nm CMOS fraction-N digi-
tal PLL with shaped in-band phase noise," in Nordic Circuits and Sys-
temsConference(NORCAS):NORCHIP&InternationalSymposiumon
System-on-Chip(SoC),2015. IEEE,2015,pp. 1-4.
Contributions. I performed a large part of the PLL modeling, simula-
tion,implementation,andlayoutdesign.Iwrotemostofthemanuscript.
ix