Table Of Content

(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3) (cid:3) (cid:3) (cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3) (cid:3) (cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3) (cid:383) (cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:40)(cid:47)(cid:40)(cid:38)(cid:55)(cid:53)(cid:50)(cid:49)(cid:76)(cid:59) (cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:69)(cid:72)(cid:70)(cid:68)(cid:88)(cid:86)(cid:72)(cid:3)(cid:90)(cid:72)(cid:3)(cid:79)(cid:76)(cid:78)(cid:72)(cid:3)(cid:76)(cid:87)(cid:3)(cid:73)(cid:82)(cid:85)(cid:3)(cid:73)(cid:85)(cid:72)(cid:72)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3) (cid:3) (cid:3) (cid:3) (cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3) Digital Logic and Microprocessor Design With VHDL Enoch O. Hwang La Sierra University, Riverside (cid:139)(cid:3)(cid:3)(cid:37)(cid:85)(cid:82)(cid:82)(cid:78)(cid:86)(cid:3)(cid:18)(cid:3)(cid:38)(cid:82)(cid:79)(cid:72)(cid:3)(cid:21)(cid:19)(cid:19)(cid:24)(cid:3) (cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:44)(cid:54)(cid:37)(cid:49)(cid:29)(cid:3)(cid:19)(cid:16)(cid:24)(cid:22)(cid:23)(cid:16)(cid:23)(cid:25)(cid:24)(cid:28)(cid:22)(cid:16)(cid:24) (cid:3) (cid:383)(cid:3)(cid:55)(cid:72)(cid:68)(cid:80)(cid:3)(cid:40)(cid:47)(cid:40)(cid:38)(cid:55)(cid:53)(cid:50)(cid:49)(cid:76)(cid:59)(cid:3)(cid:21)(cid:19)(cid:19)(cid:23) (cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3)(cid:3) To my wife and children, Windy, Jonathan and Michelle Contents Contents....................................................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:24) Preface...................................................................................................................................................................(cid:17)(cid:17)(cid:17)(cid:17)(cid:3)(cid:20)(cid:22) Chapter 1 Designing Microprocessors......................................................................................(cid:3)(cid:20)(cid:25) 1.1 Overview of a Microprocessor.......................................................................................................................(cid:3)(cid:20)(cid:26) 1.2 Design Abstraction Levels..............................................................................................................................(cid:3)(cid:21)(cid:19) 1.3 Examples of a 2-to-1 Multiplexer...................................................................................................................(cid:3)(cid:21)(cid:19) 1.3.1 Behavioral Level....................................................................................................................................(cid:3)(cid:21)(cid:20) 1.3.2 Gate Level..............................................................................................................................................(cid:3)(cid:21)(cid:21) 1.3.3 Transistor Level.....................................................................................................................................(cid:3)(cid:21)(cid:22) 1.4 Introduction to VHDL....................................................................................................................................(cid:3)(cid:21)(cid:22) 1.5 Synthesis.......................................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:25) 1.6 Going Forward..............................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:25) 1.7 Summary Checklist.......................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:26) 1.8 Problems.......................................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:26) (cid:3) Chapter 2 Digital Circuits..........................................................................................................2(cid:28) 2.1 Binary Numbers..............................................................................................................................................3(cid:19) 2.2 Binary Switch.................................................................................................................................................(cid:3)(cid:22)(cid:21) 2.3 Basic Logic Operators and Logic Expressions...............................................................................................(cid:3)(cid:22)(cid:22) 2.4 Truth Tables....................................................................................................................................................(cid:3)(cid:22)(cid:23) 2.5 Boolean Algebra and Boolean Function.........................................................................................................(cid:3)(cid:22)(cid:24) 2.5.1 Boolean Algebra....................................................................................................................................(cid:3)(cid:22)(cid:24) 2.5.2 * Duality Principle...............................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:26) 2.5.3 Boolean Function and the Inverse........................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:26) 2.6 Minterms and Maxterms...............................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:19) 2.6.1 Minterms..............................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:19) 2.6.2 * Maxterms..........................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:21) 2.7 Canonical, Standard, and non-Standard Forms.............................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:22) 2.8 Logic Gates and Circuit Diagrams................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:23) 2.9 Example: Designing a Car Security System.................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:25) 2.10 VHDL for Digital Circuits............................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:27) 2.10.1 VHDL code for a 2-input NAND gate.................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:27) 2.10.2 VHDL code for a 3-input NOR gate....................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:28) 2.10.3 VHDL code for a function...................................................................................................................(cid:17)(cid:17)(cid:3)(cid:24)(cid:19) 2.11 Summary Checklist.......................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:24)(cid:20) 2.12 Problems.......................................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:24)(cid:21) (cid:3) Chapter 3 Combinational Circuits............................................................................................(cid:3)(cid:24)(cid:28) 3.1 Analysis of Combinational Circuits................................................................................................................(cid:3)(cid:25)(cid:19) 3.1.1 Using a Truth Table...............................................................................................................................(cid:3)(cid:25)(cid:19) 3.1.2 Using a Boolean Function......................................................................................................................(cid:3)(cid:25)(cid:22) 3.2 Synthesis of Combinational Circuits..............................................................................................................(cid:3)(cid:25)(cid:23) 3.3 * Technology Mapping...................................................................................................................................(cid:3)(cid:25)(cid:25) 3.4 Minimization of Combinational Circuits......................................................................................................(cid:17)(cid:17)(cid:3)(cid:25)(cid:28) 3.4.1 Karnaugh Maps....................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:25)(cid:28) 3.4.2 Don’t-cares..........................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:26)(cid:23) 3.4.3 * Tabulation Method............................................................................................................................(cid:17)(cid:17)(cid:3)(cid:26)(cid:24) 3.5 * Timing Hazards and Glitches....................................................................................................................(cid:17)(cid:17)(cid:3)(cid:26)(cid:25) 5 3.5.1 Using Glitches.....................................................................................................................................(cid:17)(cid:17)(cid:17)(cid:17)(cid:3)(cid:26)(cid:27) 3.6 BCD to 7-Segment Decoder.........................................................................................................................(cid:17)(cid:17)(cid:17)(cid:17)(cid:3)(cid:26)(cid:27) 3.7 VHDL for Combinational Circuits...............................................................................................................(cid:17)(cid:17)(cid:17)(cid:17)(cid:3)(cid:27)(cid:19) 3.7.1 Structural BCD to 7-Segment Decoder................................................................................................(cid:17)(cid:17)(cid:17)(cid:17)(cid:3)(cid:27)(cid:20) 3.7.2 Dataflow BCD to 7-Segment Decoder................................................................................................(cid:17)(cid:17)(cid:17)(cid:17)(cid:3)(cid:27)(cid:24) 3.7.3 Behavioral BCD to 7-Segment Decoder..............................................................................................(cid:17)(cid:17)(cid:17)(cid:17)(cid:3)(cid:27)(cid:24) 3.8 Summary Checklist.......................................................................................................................................(cid:17)(cid:17)(cid:17)(cid:17)(cid:3)(cid:27)(cid:26) 3.9 Problems.......................................................................................................................................................(cid:17)(cid:17)(cid:17)(cid:17)(cid:3)(cid:27)(cid:27) (cid:3) Chapter 4 Standard Combinational Components...................................................................(cid:3)(cid:20)(cid:19)(cid:20) 4.1 Signal Naming Conventions...........................................................................................................................(cid:3)(cid:20)(cid:19)(cid:21) 4.2 Adder..............................................................................................................................................................(cid:3)(cid:20)(cid:19)(cid:21) 4.2.1 Full Adder..............................................................................................................................................(cid:3)(cid:20)(cid:19)(cid:21) 4.2.2 Ripple-carry Adder................................................................................................................................(cid:3)(cid:20)(cid:19)(cid:23) 4.2.3 * Carry-lookahead Adder.......................................................................................................................(cid:3)(cid:20)(cid:19)(cid:24) 4.3 Two’s Complement Binary Numbers.............................................................................................................(cid:3)(cid:20)(cid:19)(cid:25) 4.4 Subtractor........................................................................................................................................................(cid:3)(cid:20)(cid:19)(cid:27) 4.5 Adder-Subtractor Combination.....................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:20)(cid:19) 4.6 Arithmetic Logic Unit...................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:20)(cid:21) 4.7 Decoder.........................................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:20)(cid:26) 4.8 Encoder.........................................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:20)(cid:28) 4.8.1 * Priority Encoder................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:21)(cid:19) 4.9 Multiplexer...................................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:21)(cid:19) 4.9.1 * Using Multiplexers to Implement a Function...................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:21)(cid:22) 4.10 Tri-state Buffer.............................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:21)(cid:22) 4.11 Comparator...................................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:21)(cid:24) 4.12 Shifter...........................................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:21)(cid:27) 4.12.1 * Barrel Shifter....................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:22)(cid:19) 4.13 * Multiplier...................................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:22)(cid:19) 4.14 Summary Checklist.......................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:22)(cid:21) 4.15 Problems.......................................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:22)(cid:22) (cid:3) Chapter 5 * Implementation Technologies.............................................................................(cid:17)(cid:3)(cid:20)(cid:23)(cid:24) 5.1 Physical Abstraction.......................................................................................................................................(cid:3)(cid:20)(cid:23)(cid:25) 5.2 Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)..................................................................(cid:20)(cid:23)(cid:26) 5.3 CMOS Logic...................................................................................................................................................(cid:3)(cid:20)(cid:23)(cid:27) 5.4 CMOS Circuits...............................................................................................................................................(cid:3)(cid:20)(cid:23)(cid:28) 5.4.1 CMOS Inverter......................................................................................................................................(cid:3)(cid:20)(cid:23)(cid:28) 5.4.2 CMOS NAND gate................................................................................................................................(cid:3)(cid:20)(cid:24)(cid:19) 5.4.3 CMOS AND gate...................................................................................................................................(cid:3)(cid:20)(cid:24)(cid:20) 5.4.4 CMOS NOR and OR Gates................................................................................................................(cid:17)(cid:17)(cid:17)1(cid:24)(cid:22) 5.4.5 Transmission Gate...............................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:24)(cid:22) 5.4.6 2-input Multiplexer CMOS Circuit.....................................................................................................(cid:17)(cid:17)(cid:17)(cid:3)1(cid:24)(cid:22) 5.4.7 CMOS XOR and XNOR Gates............................................................................................................(cid:17)(cid:17)(cid:3)1(cid:24)(cid:24) 5.5 Analysis of CMOS Circuits.........................................................................................................................(cid:17)(cid:17).1(cid:24)(cid:25) 5.6 Using ROMs to Implement a Function........................................................................................................(cid:17)(cid:17).15(cid:26) 5.7 Using PLAs to Implement a Function..........................................................................................................(cid:17)(cid:17)1(cid:24)(cid:28) 5.8 Using PALs to Implement a Function..........................................................................................................(cid:17)(cid:17)(cid:3)1(cid:25)(cid:22) 5.9 Complex Programmable Logic Device (CPLD)...........................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:25)(cid:24) 5.10 Field Programmable Gate Array (FPGA).....................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:25)(cid:26) 5.11 Summary Checklist.......................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:25)(cid:27) 5.12 Problems.......................................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:25)(cid:27) 6 Chapter 6 Latches and Flip-Flops............................................................................................(cid:3)(cid:20)(cid:26)(cid:24) 6.1 Bistable Element.............................................................................................................................................(cid:3)(cid:20)(cid:26)(cid:25) 6.2 SR Latch.........................................................................................................................................................(cid:3)(cid:20)(cid:26)(cid:26) 6.3 SR Latch with Enable.....................................................................................................................................(cid:3)(cid:20)(cid:26)(cid:28) 6.4 D Latch...........................................................................................................................................................(cid:3)(cid:20)(cid:27)(cid:19) 6.5 D Latch with Enable.......................................................................................................................................(cid:3)(cid:20)(cid:27)(cid:20) 6.6 Clock...............................................................................................................................................................(cid:3)(cid:20)(cid:27)(cid:21) 6.7 D Flip-Flop..................................................................................................................................................(cid:17)(cid:17).1(cid:27)(cid:22) 6.7.1 * Alternative Smaller Circuit...............................................................................................................(cid:17)(cid:17)1(cid:27)(cid:23) 6.8 D Flip-Flop with Enable...............................................................................................................................(cid:17)(cid:17)1(cid:27)(cid:24) 6.9 Asynchronous Inputs....................................................................................................................................(cid:17)(cid:17)1(cid:27)(cid:25) 6.10 Description of a Flip-Flop............................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:27)(cid:26) 6.10.1 Characteristic Table.............................................................................................................................(cid:17)(cid:17)1(cid:27)(cid:26) 6.10.2 Characteristic Equation........................................................................................................................(cid:17)(cid:17)1(cid:27)(cid:26) 6.10.3 State Diagram......................................................................................................................................(cid:17)(cid:17)1(cid:27)(cid:27) 6.10.4 Excitation Table...................................................................................................................................(cid:17)(cid:17)1(cid:27)(cid:27) 6.11 Timing Issues................................................................................................................................................(cid:17)(cid:17)1(cid:27)(cid:27) 6.12 Example: Car Security System – Version 2..................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:27)(cid:28) 6.13 VHDL for Latches and Flip-Flops................................................................................................................(cid:17)(cid:17)1(cid:28)(cid:19) 6.13.1 Implied Memory Element....................................................................................................................(cid:17)(cid:17)1(cid:28)(cid:19) 6.13.2 VHDL Code for a D Latch with Enable..............................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:28)(cid:20) 6.13.3 VHDL Code for a D Flip-Flop...........................................................................................................(cid:17)(cid:17).19(cid:20) 6.13.4 VHDL Code for a D Flip-Flop with Enable and Asynchronous Set and Clear...................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:28)(cid:23) 6.14 * Flip-Flop Types.........................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:28)(cid:24) 6.14.1 SR Flip-Flop........................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:28)(cid:24) 6.14.2 JK Flip-Flop.........................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:28)(cid:25) 6.14.3 T Flip-Flop...........................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:28)(cid:26) 6.15 Summary Checklist.......................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:28)(cid:27) 6.16 Problems.......................................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:20)(cid:28)(cid:28) (cid:3) Chapter 7 Sequential Circuits...................................................................................................2(cid:19)(cid:20) 7.1 Finite-State-Machine (FSM) Models..............................................................................................................(cid:3)(cid:21)(cid:19)(cid:21) 7.2 State Diagrams................................................................................................................................................(cid:3)(cid:21)(cid:19)(cid:23) 7.3 Analysis of Sequential Circuits.......................................................................................................................(cid:3)(cid:21)(cid:19)(cid:26) 7.3.1 Excitation Equation...............................................................................................................................(cid:3)(cid:21)(cid:19)(cid:26) 7.3.2 Next-state Equation...............................................................................................................................(cid:3)(cid:21)(cid:19)(cid:27) 7.3.3 Next-state Table.....................................................................................................................................(cid:3)(cid:21)(cid:19)(cid:27) 7.3.4 Output Equation...................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:19)(cid:28) 7.3.5 Output Table........................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:19)(cid:28) 7.3.6 State Diagram.....................................................................................................................................(cid:17)(cid:17).(cid:3)(cid:21)0(cid:28) 7.3.7 Example: Analysis of a Moore FSM...................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:20)(cid:19) 7.3.8 Example: Analysis of a Mealy FSM....................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:20)(cid:21) 7.4 Synthesis of Sequential Circuits...................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:20)(cid:23) 7.4.1 State Diagram......................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:20)(cid:23) 7.4.2 Next-state Table...................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:20)(cid:24) 7.4.3 Implementation Table..........................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:20)(cid:26) 7.4.4 Excitation Equation and Next-state Circuit.........................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:20)(cid:27) 7.4.5 Output Table and Equation.................................................................................................................(cid:17)(cid:17).(cid:21)1(cid:27) 7.4.6 FSM Circuit.........................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:20)(cid:27) 7.4.7 Examples: Synthesis of Moore FSMs..................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:20)(cid:27) 7.4.8 Example: Synthesis of a Mealy FSM...................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:21)(cid:23) 7.5 Unused State Encodings and the Encoding of States....................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:21)(cid:25) 7.6 Example: Car Security System – Version 3..................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:21)(cid:27) 7.7 VHDL for Sequential Circuits......................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:21)(cid:28) 7 7.8 * Optimization for Sequential Circuits.........................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:22)(cid:24) 7.8.1 State Reduction...................................................................................................................................(cid:17)(cid:17).(cid:21)3(cid:24) 7.8.2 State Encoding.....................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:22)(cid:25) 7.8.3 Choice of Flip-Flops............................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:22)(cid:26) 7.9 Summary Checklist.......................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:22)(cid:28) 7.10 Problems.......................................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:23)(cid:19) (cid:3) Chapter 8 Standard Sequential Components..........................................................................2(cid:25)(cid:19) 8.1 Registers.........................................................................................................................................................(cid:3)(cid:21)(cid:25)(cid:20) 8.2 Shift Registers.................................................................................................................................................(cid:3)(cid:21)(cid:25)(cid:22) 8.2.1 Serial-to-Parallel Shift Register.............................................................................................................(cid:3)(cid:21)(cid:25)(cid:22) 8.2.2 Serial-to-Parallel and Parallel-to-Serial Shift Register..........................................................................(cid:3)(cid:21)(cid:25)(cid:24) 8.3 Counters..........................................................................................................................................................(cid:3)(cid:21)(cid:25)(cid:26) 8.3.1 Binary Up Counter.................................................................................................................................(cid:3)(cid:21)(cid:25)(cid:27) 8.3.2 Binary Up-Down Counter....................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:26)(cid:19) 8.3.3 Binary Up-Down Counter with Parallel Load.....................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:26)(cid:21) 8.3.4 BCD Up Counter.................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:26)(cid:22) 8.3.5 BCD Up-Down Counter......................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:26)(cid:23) 8.4 Register Files................................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:26)(cid:25) 8.5 Static Random Access Memory....................................................................................................................(cid:17)(cid:17)2(cid:27)(cid:19) 8.6 * Larger Memories.......................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:27)(cid:23) 8.6.1 More Memory Locations.....................................................................................................................(cid:17)(cid:17)2(cid:27)(cid:23) 8.6.2 Wider Bit Width..................................................................................................................................(cid:17)(cid:17)2(cid:27)(cid:23) 8.7 Summary Checklist.......................................................................................................................................(cid:17)(cid:17)2(cid:27)(cid:26) 8.8 Problems.......................................................................................................................................................(cid:17)(cid:17)2(cid:27)(cid:26) (cid:3) Chapter 9 Datapaths..................................................................................................................2(cid:27)(cid:28) 9.1 Designing Dedicated Datapaths......................................................................................................................(cid:3)(cid:21)(cid:28)(cid:20) 9.1.1 Selecting Registers.................................................................................................................................(cid:3)(cid:21)(cid:28)(cid:23) 9.1.2 Selecting Functional Units.....................................................................................................................(cid:3)(cid:21)(cid:28)(cid:24) 9.1.3 Data Transfer Methods..........................................................................................................................(cid:3)(cid:21)(cid:28)(cid:25) 9.1.4 Generating Status Signals....................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:28)(cid:26) 9.2 Using Dedicated Datapaths...........................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:28)(cid:27) 9.3 Examples of Dedicated Datapaths................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:28)(cid:27) 9.3.1 Simple IF-THEN-ELSE.......................................................................................................................(cid:17)(cid:17)(cid:3)(cid:21)(cid:28)(cid:28) 9.3.2 Counting 1 to 10..................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:19)(cid:19) 9.3.3 Summation of n down to 1...................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:19)(cid:21) 9.3.4 Factorial...............................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:19)(cid:22) 9.3.5 Count Zero-One...................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:19)(cid:24) 9.4 General Datapaths.........................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:19)(cid:26) 9.5 Using General Datapaths..............................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:19)(cid:27) 9.6 A More Complex General Datapath.............................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:20)(cid:19) 9.7 Timing Issues................................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:20)(cid:23) 9.8 VHDL for Datapaths.....................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:20)(cid:25) 9.8.1 Dedicated Datapath..............................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:20)(cid:25) 9.8.2 General Datapath.................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:20)(cid:26) 9.9 Summary Checklist.......................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:21)(cid:21) 9.10 Problems.......................................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:21)(cid:21) (cid:3) Chapter 10 Control Units............................................................................................................(cid:3)(cid:22)(cid:21)(cid:27) 10.1 Constructing the Control Unit.........................................................................................................................(cid:3)(cid:22)(cid:22)(cid:19) 10.2 Examples........................................................................................................................................................(cid:3)(cid:22)(cid:22)(cid:19) 8 10.2.1 Count 1 to 10.........................................................................................................................................(cid:3)(cid:22)(cid:22)(cid:19) 10.2.2 Summation of 1 to n..............................................................................................................................(cid:3)(cid:22)(cid:22)(cid:23) 10.3 Generating Status Signals.............................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:23)(cid:19) 10.4 Timing Issues................................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:23)(cid:21) 10.5 Standalone Controllers..................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:23)(cid:27) 10.5.1 Rotating Lights....................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:23)(cid:27) 10.5.2 PS/2 Keyboard Controller....................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:24)(cid:21) 10.5.3 VGA Monitor Controller.....................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:24)6 10.6 * ASM Charts and State Action Tables.......................................................................................................(cid:17)(cid:17).3(cid:25)7 10.6.1 ASM Charts........................................................................................................................................(cid:17)(cid:17)(cid:17)(cid:3)3(cid:25)7 10.6.2 State Action Tables..............................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:26)0 10.7 VHDL for Control Units...............................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:26)1 10.8 Summary Checklist.......................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:26)2 10.9 Problems.......................................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:26)4 (cid:3) Chapter 11 Dedicated Microprocessors.....................................................................................(cid:3)(cid:22)(cid:26)(cid:27) 11.1 Manual Construction of a Dedicated Microprocessor....................................................................................(cid:3)(cid:22)(cid:27)(cid:19) 11.2 Examples........................................................................................................................................................(cid:3)(cid:22)(cid:27)(cid:23) 11.2.1 Greatest Common Divisor.....................................................................................................................(cid:3)(cid:22)(cid:27)(cid:23) 11.2.2 Summing Input Numbers.....................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:28)(cid:19) 11.2.3 High-Low Guessing Game..................................................................................................................(cid:17)(cid:17)(cid:3)(cid:22)(cid:28)(cid:24) 11.2.4 Finding Largest Number......................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:19)(cid:20) 11.3 VHDL for Dedicated Microprocessors.........................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:19)(cid:25) 11.3.1 FSM + D Model...................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:19)(cid:25) 11.3.2 FSMD Model.......................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:20)(cid:20) 11.3.3 Behavioral Model................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:20)(cid:22) 11.4 Summary Checklist.......................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:20)(cid:23) 11.5 Problems.......................................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:20)(cid:23) (cid:3) Chapter 12 General-Purpose Microprocessors.........................................................................(cid:3)(cid:23)(cid:21)(cid:21) 12.1 Overview of the CPU Design.........................................................................................................................(cid:3)(cid:23)(cid:21)(cid:22) 12.2 The EC-1 General-Purpose Microprocessor...................................................................................................(cid:3)(cid:23)(cid:21)(cid:23) 12.2.1 Instruction Set........................................................................................................................................(cid:3)(cid:23)(cid:21)(cid:23) 12.2.2 Datapath.................................................................................................................................................(cid:23)(cid:21)5 12.2.3 Control Unit...........................................................................................................................................(cid:3)(cid:23)(cid:21)(cid:25) 12.2.4 Complete Circuit....................................................................................................................................(cid:3)(cid:23)(cid:21)(cid:28) 12.2.5 Sample Program...................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:22)0 12.2.6 Simulation............................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:22)(cid:21) 12.2.7 Hardware Implementation...................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:22)2 12.3 The EC-2 General-Purpose Microprocessor.................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:22)3 12.3.1 Instruction Set......................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:22)(cid:22) 12.3.2 Datapath...............................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:22)4 12.3.3 Control Unit.........................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:22)5 12.3.4 Complete Circuit..................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:22)8 12.3.5 Sample Program...................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:22)9 12.3.6 Hardware Implementation...................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:23)1 12.4 VHDL for General-Purpose Microprocessors..............................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:23)2 12.4.1 Structural FSM+D...............................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:23)2 12.4.2 Behavioral FSMD................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:23)9 12.5 Summary Checklist.......................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:24)2 12.6 Problems.......................................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:24)2 9 Appendix A Schematic Entry Tutorial 1....................................................................................(cid:3)(cid:23)(cid:24)(cid:25) A.1 Getting Started................................................................................................................................................(cid:3)(cid:23)(cid:24)(cid:25) A.1.1 Preparing a Folder for the Project..........................................................................................................(cid:3)(cid:23)(cid:24)(cid:25) A.1.2 Starting MAX+plus II............................................................................................................................(cid:3)(cid:23)(cid:24)(cid:25) A.1.3 Starting the Graphic Editor....................................................................................................................(cid:3)(cid:23)(cid:24)(cid:26) A.2 Using the Graphic Editor................................................................................................................................4(cid:24)(cid:27) A.2.1 Drawing Tools.......................................................................................................................................4(cid:24)(cid:27) A.2.2 Inserting Logic Symbols........................................................................................................................4(cid:24)(cid:27) A.2.3 Selecting, Moving, Copying, and Deleting Logic Symbols...................................................................(cid:3)(cid:23)(cid:24)(cid:28) A.2.4 Making and Naming Connections.........................................................................................................(cid:23)6(cid:19) A.2.5 Selecting, Moving and Deleting Connection Lines...............................................................................(cid:3)(cid:23)(cid:25)(cid:21) A.3 Specifying the Top-Level File and Project.....................................................................................................(cid:3)(cid:23)(cid:25)(cid:21) A.3.1 Saving the Schematic Drawing..............................................................................................................(cid:3)(cid:23)(cid:25)(cid:21) A.3.2 Specifying the Project............................................................................................................................(cid:3)(cid:23)(cid:25)(cid:21) A.4 Synthesis for Functional Simulation...............................................................................................................(cid:3)(cid:23)(cid:25)(cid:21) A.5 Circuit Simulation...........................................................................................................................................(cid:3)(cid:23)(cid:25)(cid:22) A.5.1 Selecting Input Test Signals..................................................................................................................(cid:3)(cid:23)(cid:25)(cid:22) A.5.2 Customizing the Waveform Editor......................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:25)(cid:23) A.5.3 Assigning Values to the Input Signals.................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:25)(cid:24) A.5.4 Saving the Waveform File...................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:25)(cid:24) A.5.5 Starting the Simulator..........................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:25)(cid:25) A.6 Creating and Using the Logic Symbol..........................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:25)(cid:26) (cid:3) Appendix B VHDL Entry Tutorial 2...........................................................................................(cid:3)(cid:23)(cid:25)(cid:27) B.1 Getting Started................................................................................................................................................(cid:3)(cid:23)(cid:25)(cid:27) B.1.1 Preparing a Folder for the Project..........................................................................................................(cid:3)(cid:23)(cid:25)(cid:27) B.1.2 Starting MAX+plus II............................................................................................................................(cid:3)(cid:23)(cid:25)(cid:27) B.1.3 Creating a Project..................................................................................................................................(cid:3)(cid:23)(cid:25)(cid:28) B.1.4 Editing the VHDL Source Code............................................................................................................(cid:3)(cid:23)(cid:26)(cid:19) B.2 Synthesis for Functional Simulation...............................................................................................................(cid:3)(cid:23)(cid:26)(cid:19) B.3 Circuit Simulation...........................................................................................................................................(cid:3)(cid:23)(cid:26)(cid:20) B.3.1 Selecting Input Test Signals..................................................................................................................(cid:3)(cid:23)(cid:26)(cid:20) B.3.2 Customizing the Waveform Editor........................................................................................................(cid:3)(cid:23)(cid:26)(cid:22) B.3.3 Assigning Values to the Input Signals...................................................................................................(cid:3)(cid:23)(cid:26)(cid:22) B.3.4 Saving the Waveform File.....................................................................................................................(cid:3)(cid:23)(cid:26)(cid:23) B.3.5 Starting the Simulator............................................................................................................................(cid:3)(cid:23)(cid:26)(cid:23) (cid:3) Appendix C UP2 Programming Tutorial 3.................................................................................(cid:3)(cid:23)(cid:26)(cid:25) C.1 Getting Started................................................................................................................................................(cid:3)(cid:23)(cid:26)(cid:25) C.1.1 Preparing a Folder for the Project..........................................................................................................(cid:3)(cid:23)(cid:26)(cid:25) C.1.2 Creating a Project..................................................................................................................................(cid:3)(cid:23)(cid:26)(cid:26) C.1.3 Viewing the Source File........................................................................................................................(cid:3)(cid:23)(cid:26)(cid:26) C.2 Synthesis for Programming the PLD..............................................................................................................(cid:3)(cid:23)(cid:26)(cid:26) C.3 Circuit Simulation...........................................................................................................................................(cid:3)(cid:23)(cid:26)(cid:27) C.4 Using the Floorplan Editor.............................................................................................................................(cid:3)(cid:23)(cid:27)(cid:19) C.4.1 Selecting the Target Device...................................................................................................................(cid:3)(cid:23)(cid:27)(cid:19) C.4.2 Maping the I/O Pins with the Floorplan Editor......................................................................................(cid:3)(cid:23)(cid:27)(cid:20) C.5 Fitting the Netlist and Pins to the PLD...........................................................................................................(cid:3)(cid:23)(cid:27)(cid:22) C.6 Hardware Setup............................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:27)(cid:23) C.6.1 Installing the ByteBlaster Driver.........................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:27)(cid:23) C.6.2 Jumper Settings....................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:27)(cid:23) C.6.3 Hardware Connections........................................................................................................................(cid:17)(cid:17)(cid:17)(cid:3)(cid:23)(cid:27)(cid:23) C.7 Programming the PLD..................................................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:27)(cid:24) C.8 Testing the Hardware......................................... ...........................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:27)(cid:25) C.9 MAX7000S EPM7128SLC84-7 Summary...................................................................................................(cid:17)(cid:17)(cid:3)(cid:23)(cid:27)(cid:26) 10

Digital Logic and Microprocessor Design With VHDL PDF

513 Pages·2005·5.625 MB·English

by Enoch O. Hwang

#Technique #Electronics: Microprocessor Technology

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Author:	Enoch O. Hwang
Publication Year:	2005
ISBN:	534465935
Pages:	513
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