Development of Quantum Annealing Technology at D-Wave Systems

25 Pages·2017·5.28 MB·English

by  Trevor Lanting

Development of Quantum
Annealing Technology at
D-Wave Systems
Trevor Lanting
November 29, 2017
Overview
(cid:73) Why Quantum Annealing?
(cid:73) Processor Design and Manufacturing
(cid:73) Using the System
Copyright©D-WaveSystemsInc. 1/19
Building a Large-Scale Quantum Technology
(cid:73) scalability directly
informs implementation
details
(cid:73) device design tightly
coupled with control
infrastructure
(cid:73) general in situ tunability
required
(cid:73) manufacturing →
leverage CMOS
techniques
Copyright©D-WaveSystemsInc. 2/19
Quantum Annealing - What is it?
GOAL: find ground state or low energy configurations of the Ising model
(cid:73) quantum annealing proposed as an algorithm for finding ground state
configurations of this model PRE 58, 5355 (1998)
(cid:73) H(t) = ∆(t)H +E(t)H
initial target
(cid:73) begin with ∆(t) (cid:29) E(t), evolve Hamiltonian to ∆(t) (cid:28) E(t)
y
g
r
e
n
E
local
minimum
global problem variables
minimum
Copyright©D-WaveSystemsInc. 3/19
Quantum Annealing - Why?
Build systems expertise in developing a large-scale commercially-viable quantum
technology
(cid:73) slow control over annealing time scales → no
7 Γ 1 Γ∼1 Γ 1
fast microwaves routed to every device
6
(cid:73) QA Hamiltonian is “on” during the entire
evolution z)5
H
G
(cid:73) exploiting tendency of systems to evolve to low (04
E
energy configurations −3
E
(cid:73) persistent entanglement even at equilibrium 2
(cid:73) Phys.Rev.X4,021041(2014)
1
kBT
0
0.6 0.65 0.7
Φccjj/Φ0
Copyright©D-WaveSystemsInc. 4/19
Quantum Annealing - Why?
What can you do with an algorithm that returns optimal or low energy solutions of a
programmable Ising spin system? almost everything!
Kochenberger,G.etal,JCombOptim28.1(2014):58-81
(cid:73) machine learning
(cid:73) satisfiability
(cid:73) materials simulation
(cid:34) (cid:35)
HQSG(t) = E(t) −∑hiσz(i)+ ∑ Jijσz(i)σz(j) −∆(t)∑σx(i) . (1)
i i,j>i i
h and J are in situ tunable → huge space of problems can be mapped onto this
i ij
Hamiltonian
e.g.T.KadowakiandH.Nishimori,PRE,58(5),pp.5355-5363,(1998),
orE.Farhi,etal.,Science292,472(2001)fordetails.
Copyright©D-WaveSystemsInc. 5/19
Flux Qubit → Quantum Ising spin
aΦ1X "spin-up" circulating current U b
B
ll
Φ 1
Φ2X "spin-down" circulating current δU
Φ 2 2h Bt
Φ
Jojusenpcthiosonn 1
Hq = −12 (cid:2)(cid:101)qσz+∆qσx(cid:3) HQS = −gµB(cid:2)B||σz+Btσx(cid:3)
where (cid:101)q = 2(cid:12)(cid:12)Iqp(cid:12)(cid:12)Φxq = −hiσz− 12∆σx
Parameter Qubit Quantum Ising Spin
Bias Energy (cid:101) /2 gµ B or h
q B ||
Tunneling Energy ∆ /2 gµ B
q B t
Moment Ip gµ
q B
Binary information encoded in flux basis: |0(cid:105) → |↓(cid:105) and |1(cid:105) → |↑(cid:105).
Copyright©D-WaveSystemsInc. 6/19
Two Coupled Qubits
(cid:73) flux Φx controls energy bias (cid:101) = 2|Ip|Φx between |↓(cid:105) and |↑(cid:105), provided by local
1 q 1
DAC
(cid:73) flux bias Φx controls barrier height (∆) → provided by global line
2
(cid:73) E(s) = M |Ip(s)|2
AFM q
(cid:73) ∆ and |Ip| change with s
q
(cid:73) M is in situ tunable
eff
Copyright©D-WaveSystemsInc. 7/19
X/Y/Z addressing scheme uses 80 wires to address 20,000 DAC “loops”
SeeBunyketal.,arXiv:1401.5504(2014),
orJohnsonetal.,Supercond.Sci.Technol.23,065004(2010)
A Scalable QA Processor Architecture
In this architecture, a 2000 Q processor requires ∼ 20,000 bias signals,
(cid:73) only 150 differential biased pairs passed to the chip via wirebonds
(cid:73) Local flux biases applied by on-chip flux-DAC’s
Use on-chip DAC’s to:
(cid:73) Program {h},(cid:8)J (cid:9)
i ij
(cid:73) homogenize devices
(cid:73) coerce Ising behaviour
Copyright©D-WaveSystemsInc. 8/19
X/Y/Z addressing scheme uses 80 wires to address 20,000 DAC “loops”
SeeBunyketal.,arXiv:1401.5504(2014),
orJohnsonetal.,Supercond.Sci.Technol.23,065004(2010)
A Scalable QA Processor Architecture
In this architecture, a 2000 Q processor requires ∼ 20,000 bias signals,
(cid:73) only 150 differential biased pairs passed to the chip via wirebonds
(cid:73) Local flux biases applied by on-chip flux-DAC’s
Use on-chip DAC’s to:
(cid:73) Program {h},(cid:8)J (cid:9)
i ij
(cid:73) homogenize devices
(cid:73) coerce Ising behaviour
Copyright©D-WaveSystemsInc. 8/19