Design Techniques for Analog-to-Digital Converters in Scaled CMOS Technologies

161 Pages·2016·8.51 MB·English

Design Techniques for Analog-to-Digital
Converters in Scaled CMOS Technologies
Jayanth Kuppambatti
Submitted in partial fulfillment of the
requirements for the degree of
Doctor of Philosophy
in the Graduate School of Arts and Sciences
COLUMBIA UNIVERSITY
2014
©2014
JayanthKuppambatti
AllRightsReserved
Abstract
Design Techniques for Analog-to-Digital
Converters in Scaled CMOS Technologies
Jayanth Kuppambatti
Analog-to-digital converters (ADCs) are analog pre-processing systems that convert the real
life analog signals, the input of sensors or antenna, to digital bits that are processed by the system
digital back-end. Due to the various issues associated with CMOS technology scaling such as
reduced signal swings and lower transistor gains, the design of ADCs has seen a number of chal-
lenges in medium to high resolution and wideband digitization applications. The various chapters
of this thesis focus on efficient design techniques for ADCs that aim to address the challenges
associatedwithdesigninscaledCMOStechnologies.
Thisthesisdiscussesthedesignofthreeanalogandmixed-signalprototypes: thefirstprototype
introducescurrentpre-charging(CRP)techniquestogeneratethereferenceinMultiplyingDigital-
to-Analog Converters (MDACs) of pipeline ADCs. CRP techniques are specifically applied to
Zero-CrossingBased(ZCB)Pipeline-SARADCsinthiswork. Theproposedreferencepre-charge
techniquerelaxespowerandarearequirementsforreferencevoltagegenerationanddistributionin
ZCB Pipeline ADCs, by eliminating power hungry low impedance reference voltage buffers. The
next prototype describes the design of a radiation-hard dual-channel 12-bit 40MS/s pipeline ADC
with extended dynamic range, for use in the readout electronics upgrade for the ATLAS Liquid
ArgonCalorimetersattheCERNLargeHadronCollider. ThedesignconsistsoftwopipelineA/D
channels with four MDACs with nominal 12-bit resolution each, that are verified to be radiation-
hardbeyondtherequiredspecifications.
The final prototype proposes Switched-Mode Signal Processing, a new design paradigm that
achievesrail-to-railsignalswingswithhighlinearityatultra-lowsupplyvoltages. Switched-Mode
Signal Processing represents analog information in terms of pulse widths and replaces the out-
putstageofOTAswithpower-efficientrail-to-railClass-Dstages,thusproducingSwitched-Mode
OperationalAmplifiers(SMOAs). TheSMOAsareusedtoimplementaProgrammableGainAm-
plifier(PGA)thathasaprogrammablegainfrom0-12dB.
Contents
ListofFigures v
ListofTables xii
1 Introduction 1
1.1 CMOSTechnologyScaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Analog-to-DigitalConverters(ADCs) . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 PipelineADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.1 DigitalCalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.2 ChallengesinOTAImplementationinScaled-CMOSTechnologies . . . . 9
1.4 RecentAdvancesinMDACResidueAmplification . . . . . . . . . . . . . . . . . 11
1.4.1 CorrelatedLevelShifting . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4.2 Zero-CrossingBased(ZCB)Circuits . . . . . . . . . . . . . . . . . . . . . 15
1.5 ThesisOrganization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2 CurrentReferencePre-chargingforZero-CrossingbasedPipelinedADCs 19
i
2.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2 ImplementationChallengesforVoltageReferenceBuffers . . . . . . . . . . . . . 22
2.2.1 VoltageReferenceBuffersforOTA-basedMDACs . . . . . . . . . . . . . 22
2.2.2 AdditionalReferencePathIssuesinZCBdesigns . . . . . . . . . . . . . . 24
2.3 LowPowerCurrentReferencePre-chargingTechniques . . . . . . . . . . . . . . . 26
2.3.1 Current Reference Pre-charging (CRP) with Constant Reference Loading
(CRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3.2 InputRangeExtension(IRE) . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.3.3 CurrentReferencePre-chargingwithDynamicReferenceLoading(DRL) . 34
2.3.4 DigitalCalibrationTechniquesforCRP . . . . . . . . . . . . . . . . . . . 35
2.3.5 Non-IdealEffectsinCRP . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.4 ADCCircuitImplementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.4.1 SystemArchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.4.2 ZCBMDACImplementation . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.4.3 9-bitCurrent-ReferencePre-chargedSARADCforADC . . . . . . . . . 49
2
2.4.4 InputSamplingandClockNetworks . . . . . . . . . . . . . . . . . . . . . 51
2.5 ExperimentalResults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.5.1 MeasurementSetup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.5.2 CalibrationProcedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.5.3 ADC MeasurementResults . . . . . . . . . . . . . . . . . . . . . . . . . 54
1
2.5.4 ADC MeasurementResults . . . . . . . . . . . . . . . . . . . . . . . . . 60
2
ii
3 Radiation-hardDualChannelPipelineADCforCERNCalorimetricReadout 70
3.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.2 SystemArchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.2.1 SystemSpecifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.2.2 RadiationTolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.2.3 PrototypeImplementation . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.3 MeasurementResults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.3.1 ADCPerformance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.3.2 Irradiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.3.3 ADCPerformancePost-irradiation . . . . . . . . . . . . . . . . . . . . . . 88
3.4 GainSelection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.4.1 GainSelectionMeasurements . . . . . . . . . . . . . . . . . . . . . . . . 94
3.4.2 GainSelectionAlgorithm . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
3.6 2-Channel12-bit40MS/sPipeline-SARADC . . . . . . . . . . . . . . . . . . . . 102
3.6.1 MeasurementResults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
3.7 4-Channel12-bit40MS/sPipeline-SARADC . . . . . . . . . . . . . . . . . . . . 108
4 Ultra-LowVoltageMixed-SignalDesign: Switched-ModeSignalProcessing 109
4.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.2 LimitedVoltageHeadroominScaledCMOSTechnologies . . . . . . . . . . . . . 110
4.3 Switched-ModeOperationalAmplifiers(SMOAs) . . . . . . . . . . . . . . . . . . 113
iii
4.3.1 AdvantagesofSMOAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.3.2 SMOAModel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.3.3 SMOAOutputSpectrumandMulti-phasePWMModulation . . . . . . . . 117
4.4 Programmable-GainAmplifierusingSMOAs . . . . . . . . . . . . . . . . . . . . 119
4.4.1 8-phaseSMOAArchitecture . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.4.2 SMOAUnitCellCircuitDesign . . . . . . . . . . . . . . . . . . . . . . . 121
4.5 MeasurementResults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5 ConclusionsandFutureWork 133
5.1 FutureWork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.1.1 SeriesReferencePre-chargedMDAC . . . . . . . . . . . . . . . . . . . . 135
5.1.2 ImprovingthePerformanceofSMOAs . . . . . . . . . . . . . . . . . . . 138
Bibliography 139
iv
List of Figures
1.1 ITRSscalingroadmapfortransistorgatelengthL . . . . . . . . . . . . . . . . . . 2
g
1.2 ITRSscalingroadmapfortransistor f . . . . . . . . . . . . . . . . . . . . . . . . 2
T
1.3 ITRSscalingroadmapfordevicesupplyvoltageV . . . . . . . . . . . . . . . . 3
DD
1.4 Blockdiagramofasignalprocessingchain. . . . . . . . . . . . . . . . . . . . . . 5
1.5 Blockdiagramofa1.5-bit/stagePipelineADC. . . . . . . . . . . . . . . . . . . . 6
1.6 Typicalimplementationofa1.5-bitMDACstage. . . . . . . . . . . . . . . . . . . 7
1.7 MDAC residue characteristic (left). Reconstructed output (right); V - reference
ref
voltage;V -residuevoltage;D-subADCdecision;D -reconstructedoutput. . 8
res out
1.8 2-stageMillerOTA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.9 OTAgainvs. outputvoltageillustratinggaincompression. . . . . . . . . . . . . . 10
1.10 INLoftheMDACinFig.1.6withtheMillerOTAofFig.1.8. . . . . . . . . . . . 11
1.11 Correlatedlevelshiftingappliedtoatypical1-bit/stageMDAC. . . . . . . . . . . 12
1.12 CLS-MDAC redrawn during: (left) Estimation phase φ ; (right) Level shift phase
e
φ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
LS
1.13 WaveformattheMDACoutputV . . . . . . . . . . . . . . . . . . . . . . . . . . 13
out
v
1.14 CLSOTAloopgain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.15 CLSOTAINL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.16 1-bit/stageZCBMDAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1 Circuitimplementationofatypical1-bitMDACstage[3]withthetimingdiagram. 21
2.2 Inter-stage reference noise coupling in ZCB MDAC designs, here illustrated be-
tweenStageIandStageIII,furtherincreasesthereferencebufferrequirements. . . 25
2.3 Schematic of the current reference pre-charged 7-level ZCB MDAC architecture
(subADCpathandpre-chargeswitchesnotshown). . . . . . . . . . . . . . . . . . 27
2.4 (top) Timing diagram; (bottom) Residue characteristic for the MDAC shown in
Fig.2.3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.5 ZCB MDAC using current reference pre-charging with constant reference loading
redrawnduringtheholdphaseφ . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
h
2.6 ResiduecharacteristicforMDACwithInputRangeExtension(IRE). . . . . . . . . 32
2.7 Schematic of the pre-charged 9-level ZCB MDAC architecture with dynamic ref-
erenceloadingandinputrangeextension(subADCpathnotshown). . . . . . . . . 33
2.8 DynamicreferenceloadingMDACduringholdphasefortwosub-ADCdecisions:
(left)D=2andV =4V +2V ;(right)D=-1andV =4V -V . . . . . . . . . 34
out in ref out in ref
2.9 Digitalforegroundcalibrationofreferencegainerrorandreferencecapacitormis-
matchesinCRP:(left)Residuecharacteristic;(right)Reconstructeddigitaloutput. . 37
2.10 Architecture of the hybrid pipelined-SAR ADC (ADC ) prototype with current
1
referencepre-charging;D<16:0>aretherawADCbitsbeforedigitalcalibration. 39
vi