Design Rules in a Semiconductor Foundry

831 Pages·2022·25.764 MB·English

by  Eitan N. Shauly

Design Rules in a
Semiconductor Foundry

Design Rules in a
Semiconductor Foundry
edited by
Eitan N. Shauly
Published by
Jenny Stanford Publishing Pte. Ltd.
101 Thomson Road
#06-01, United Square
Singapore 307591
Email: [email protected]
Web: www.jennystanford.com
British Library Cataloguing-in-Publication Data
A catalogue record for this book is available from the British Library.
Design Rules in a Semiconductor Foundry
All rights reserved. This book, or parts thereof, may not be reproduced in any form
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ISBN 978-981-4968-00-3 (Hardcover)
ISBN 978-1-003-31172-0 (eBook)
Contents
Preface
Acknowledgment
xvii
Contributors
xix
1. Layout Design Rules: Definition, xxi
Setting, and Scaling 1
Eitan N. Shauly
1.1 Introduction: The Goal of Design Rules 1
1.2 Different Types of Layout DRs 4
1.2.1 The WIDTH Rule 5
1.2.2 The SPACE Rule 6
1.2.3 The DISTANCE Rule 6
1.2.4 The ENCLOSURE Rule 7
1.2.5 The EXTENSION Rule 7
1.2.6 The OVERLAP Rule 8
1.2.7 The COVERAGE Rule 8
1.2.8 The AREA1 Rule 9
1.2.9 The AREA2 Rule 9
1.2.10 The PERIPHERY Rule 9
1.2.11 The PARALLEL LENGTH Rule 10
1.2.12 The INTERACT Rule 10
1.2.13 The NOT allowed Rule 10
1.2.14 M ore Definitions and Examples
for More Complex Rules 12
1.3 Different Considerations for Setting a New DR 13
1.4 Reliability Consideration for DR Setting 19
1.5 Device Sensitivity to Layout Proximity 21
1.6 Design Ranking 24
1.7 Standard Cells Digital Density and Layout
Considerations 30
1.8 Device Considerations for Standard Cells 37
1.9 Restricted Design Rules 39
vi Contents
1.10 Gridded Design Rules 40
1.10.1 GDR (Regular-Fabric-Based) Design
Methodology 43
1.11 Double Patterning 46
1.11.1 Resolution Enhancement: the Drive
Force for DP 46
1.11.2 M ask Decomposition and Colors
Conflicts: LELE Integration 48
1.11.3 M ask Decomposition (with Line-Cut)
for SADP Integration 53
1.11.4 I nterconnect Variation Modeling
under DP Misalignment 58
1.11.5 DRC, Anchoring, and Standard Cells
Placement 59
1.11.6 Dummy Fill Insertion under
2. Front-End-of-LinDeP T oCpoonlsotgriacianls D esign Rules 6629
Eitan N. Shauly
2.1 Introduction 69
2.1.1 Minimum Area Rules (.A.1 and .A.2) 70
2.1.2 AA for Oxide Diffusion (OD) Rules 72
2.1.2.1 AA width (AA.W.1) 74
2.1.2.2 Intra-well isolation (AA.S.1) 75
2.1.2.3 Enclosed AA (AA.A.2): STI
stress-induced defectivity 77
2.1.2.4 T he dependency of gate
width and gate LER on
AA width 78
2.1.3 WN (N-well) Rules 80
2.1.3.1 N-well junction breakdown 81
2.1.3.2 N-well width (WN.W.1) and
space (WN.S.1/2) 83
2.1.3.3 N -well as a protected diode
(WN.A.1) and floating N-well
(WN.N.1) 85
2.1.3.4 Inter-well isolation
(AA.E.3, AA.D.3) 85
Contents vii
2.1.3.5 Layout considerations for
well masks 88
2.1.3.6 Well (mask) proximity
effect (WPE) 90
2.1.4 Guard Rings and DNW Rules 93
2.1.4.1 Integration of DNW 96
2.1.4.2 I solation enhancement
by native layer around
the N-well ring 102
2.1.5 Threshold Voltage Complimentary
(VTC) Implant Rules 103
2.1.5.1 Layout variability for
VTC masks 105
2.1.6 DGO Area Rules 108
2.1.6.1 V MOSFETs threshold
voltage shift 111
2.1.7 Poly GC Rules 111
2.1.7.1 Core poly width (GC.W.1) 113
2.1.7.2 C ore poly space (GC.S.1),
space over STI (GC.S.2) and
poly pitch 115
2.1.7.3 Width of poly for routing
(over STI, GC.W.2) 119
2.1.7.4 GC.D.1: distance of poly
over STI to related AA 120
2.1.7.5 Poly LER and layout sensitivity 127
2.1.7.6 GC.X.2: Extension of poly
beyond AA (endcap) 130
2.1.8 2nd Poly Mask for Poly Cut
(P2MC) Rules 130
2.1.8.1 Poly cut mask with SADP 136
3. Back-End2-.1o.f9-L ineN T+o Sp/oDlo agnicda lP D+e Ss/igDn (RNuPleSsD ) Rules 113571
Eitan N. Shauly
3.1 Introduction 151
3.1.1 Methodology for BEOL Design
Rule Setting 154
viii Contents
3.1.2 Contact Related Rules 157
3.1.2.1 Contact width and space rules 159
3.1.2.2 E nclosure and extension
of active and poly around
contact 162
3.1.2.3 Distance of S/D contact to
related gate 166
3.1.2.4 Non-square contacts 174
3.1.2.5 Optical-Proximity-Correction
for contacts 177
3.1.2.6 DRs for contact formed
by double patterning 179
3.1.3 Metal Related Rules 182
3.1.3.1 Metal width and space rules 183
3.1.3.2 Metal enclosed rules 196
3.1.4 Via Rules 200
3.1.4.1 Via width and space rules 203
3.1.4.2 Double-via and VIABAR rules 206
3.1.5 BEOL Reliability–Related Design Rules 207
3.1.5.1 M aximum current density
in metal wires and contact/
vias under DC conditions 208
3.1.5.2 S etting up design guidelines
for metal width on the basis
of EM failures 210
3.1.5.3 V ia rules as extracted from
stress-induced-voids
measurements 218
3.1.5.4 M inimum metal space
rules as extracted by TDDB
measurements 225
3.1.6 Integration for Sub-28 nm Technology:
Middle-of-Line 228
3.1.6.1 L ocal interconnects and
middle-of-line (MOL)
integration 229
3.1.6.2 Reliability of middle-of-line
interconnects 233
3.1.6.3 Air gaps for capacitance
reduction 234
Contents ix
4. Coverage Rules and Insertion Utilities 249
Eitan N. Shauly
4.1 Introduction: The Need for Planarization 249
4.2 CMP Planarization for Oxide and Cu 254
4.3 CMP Process Integration 256
4.3.1 Dishing and Erosion 256
4.3.2 STI CMP Process and the
Main Challenges 260
4.3.3 Cu CMP Process 264
4.3.4 Cu CMP Modeling 265
4.3.5 Cu Electroplating 266
4.4 Global and Local Planarization 267
4.4.1 CMP Range (Density Interaction
Distance) 267
4.5 AA, Poly, and Al Global Coverage Rules 270
4.6 AA and Copper Local Coverage Rules 274
4.7 Minimum and Maximum Copper Coverage
Design Rule Setting 277
4.8 Dummy AA, Dummy Poly, and Dummy
Metal Rules 282
4.8.1 Multilevel Coverage Integration Effects 287
4.8.2 Design-for-Manufacturing for
Copper Lines 293
4.9 Different Methods for Dummy Fill Insertion 294
4.9.1 Dummy Shapes, Tools, and Insertion
Efficiency 294
4.9.2 Single-Size Tile Filling 295
4.9.3 Rule-Based (Linear-Programing)
Dummy Fill 297
4.9.4 Model-Based Driven Dummy Fill 303
4.9.5 Net-Aware and Timing-Aware DM Fill 304
4.9.6 More Advanced Fill Methods: Cell Fill 306
4.10 Capacitive Coupling of Dummies 307
4.11 The Effect of Dummy Fill on Wire Resistance
and Inductance 312
4.12 The Effect of Dummy Fill on Inductors 315
4.13 Dummy Fill Blocking Layers 318
4.14 RTA-Aware Dummy Fill Insertion 320