Design of Silicon Power Amplifiers and Arrays for Millimeter Wave

133 Pages·2014·12.98 MB·English

by  Bassel Hanafi

UC San Diego
UC San Diego Electronic Theses and Dissertations
Title
Design of Silicon Power Ampliers and Arrays for Millimeter Wave Applications
Permalink
https://escholarship.org/uc/item/45n3721g
Author
Hanafi, Bassel
Publication Date
2014

Peer reviewed|Thesis/dissertation
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University of California
UNIVERSITY OF CALIFORNIA, SAN DIEGO
Design of Silicon Power Amplifiers and Arrays for Millimeter Wave
Applications
A dissertation submitted in partial satisfaction of the
requirements for the degree
Doctor of Philosophy
in
Electrical Engineering (Electronic Circuits and Systems)
by
Bassel Hanafi
Committee in charge:
Professor Peter M. Asbeck, Chair
Professor James F. Buckwalter
Professor Brian G. Keating
Professor Andrew C. Kummel
Professor Gabriel M. Rebeiz
2014
Copyright
Bassel Hanafi, 2014
All rights reserved.
The dissertation of Bassel Hanafi is approved, and it is
acceptable in quality and form for publication on micro-
film and electronically:
Chair
University of California, San Diego
2014
iii
DEDICATION
To my mother
iv
TABLE OF CONTENTS
Signature Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Dedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
Vita . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv
Abstract of the Dissertation . . . . . . . . . . . . . . . . . . . . . . . . . . . xvi
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Millimeter Wave Applications . . . . . . . . . . . . . . . 2
1.1.1 Automotive Radar . . . . . . . . . . . . . . . . . 3
1.1.2 Wireless High-Definition Content Transmission . . 5
1.1.3 Millimeter Wave Mobile . . . . . . . . . . . . . . 5
1.2 Silicon Power Amplifiers . . . . . . . . . . . . . . . . . . 7
1.2.1 Stacked PAs . . . . . . . . . . . . . . . . . . . . . 8
1.2.2 Power Combining . . . . . . . . . . . . . . . . . . 8
1.3 Dissertation Scope and Organization . . . . . . . . . . . 10
Chapter 2 A300mWQ-bandPowerAmplifierImplementedinSiGeBiC-
MOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 Stacking Overview . . . . . . . . . . . . . . . . . . . . . 14
2.3 Amplifier Design . . . . . . . . . . . . . . . . . . . . . . 17
2.3.1 Unit Amplifier . . . . . . . . . . . . . . . . . . . . 17
2.3.2 Amplifier Biasing . . . . . . . . . . . . . . . . . . 23
2.3.3 Power Combining . . . . . . . . . . . . . . . . . . 25
2.4 Experimental Results and Revisited Modeling . . . . . . 28
2.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 33
Chapter 3 Q-Band Spatially-Combined Power Amplifier Arrays in 45nm
CMOS SOI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2 System Overview . . . . . . . . . . . . . . . . . . . . . . 35
3.3 Chip Design . . . . . . . . . . . . . . . . . . . . . . . . . 37
v
3.3.1 PA Unit Cells - Design Considerations . . . . . . 37
3.3.2 Passive Structures and Supply Distribution . . . . 41
3.3.3 Antenna Board Design . . . . . . . . . . . . . . . 46
3.3.4 Thermal Considerations . . . . . . . . . . . . . . 50
3.4 Experimental Results . . . . . . . . . . . . . . . . . . . . 53
3.4.1 Testing of the 4-stack PA . . . . . . . . . . . . . . 53
3.4.2 Testing of the array chip . . . . . . . . . . . . . . 53
3.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.6 Appendix 3.A: Stability of Stacked FET PAs . . . . . . . 71
Chapter 4 Thermal Analysis of Millimeter-Wave Power Amplifiers Imple-
mented in CMOS SOI . . . . . . . . . . . . . . . . . . . . . . 77
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.2 Thermal Modeling . . . . . . . . . . . . . . . . . . . . . 80
4.2.1 The Back-end Oxide . . . . . . . . . . . . . . . . 84
4.2.2 Interconnects . . . . . . . . . . . . . . . . . . . . 86
4.2.3 Cross-Heating Effect . . . . . . . . . . . . . . . . 89
4.3 Experimental Verification . . . . . . . . . . . . . . . . . . 91
4.4 Full Amplifier Model . . . . . . . . . . . . . . . . . . . . 97
4.5 Thermally Aware Layout Optimization . . . . . . . . . . 100
4.6 Summary and Conclusions . . . . . . . . . . . . . . . . . 103
Chapter 5 Conclusions and Future Work . . . . . . . . . . . . . . . . . . 105
5.1 Dissertation Summary . . . . . . . . . . . . . . . . . . . 105
5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . 107
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
vi
LIST OF FIGURES
Figure 1.1: Atmospheric attenuation of mm-waves from [2] . . . . . . . . . 2
Figure 1.2: (a) Automotive radar concept as appears in [5]. (b) Housing of
a commercial radar sensor as presented in [6]. (c) PCB of the
radar with MMIC transceiver module and patch antennas on
PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 1.3: Mm-wave 5G mobile concept from [10] . . . . . . . . . . . . . . 6
Figure 1.4: Stacked mm-wave PA concept from [17] . . . . . . . . . . . . . 9
Figure 2.1: Chip combined SiGe PA comprising 16 units . . . . . . . . . . . 14
Figure 2.2: (a) Stacked-FET concept showing 3-stacked FET [16]. (b) Two
stacked-bipolar PA. (c) Small-signal model for Q2 to calculate
the emitter impedance. . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 2.3: The PA unit cell . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 2.4: Simulated time domain waveforms for the unit PA at 45 GHz . 20
Figure 2.5: Simulated time domain waveforms for 2-stacked FET PA in [17]
at 45 GHz and maximum output power . . . . . . . . . . . . . 21
Figure 2.6: Magnitude of fundamental components for Ib vs Ic and Ig
2 2 2
vs Id for stacked bipolar and FET PAs respectively . . . . . . 22
2
Figure 2.7: Simulated reverse DC base current for the bottom devices vs
output power of the unit PA . . . . . . . . . . . . . . . . . . . . 23
Figure 2.8: (a) Standard low impedance biasing circuit. (b) Proposed im-
proved biasing circuit. For this design, all devices are sized at
20×0.13 µm2, R = 312 Ω, R = 405 Ω, and Vbb = 2.2 V. . . . 24
B
Figure 2.9: Output voltage of the proposed and original bias cells at differ-
ent output currents (I = 2 mA for both cases) . . . . . . . . . 25
0
Figure 2.10: Schematicdiagramof1/2amplifier(impedancevaluesdisplayed
at 45 GHz), along with cross sections of µ-strip and grounded
CPW (G-CPW) lines . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 2.11: Large signal simulations of the initial design for 16x PA at 45 GHz 27
Figure 2.12: Die micrograph of the fabricated SiGe PA . . . . . . . . . . . . 28
Figure 2.13: Measured small-signal S-parameters vs simulations . . . . . . . 29
Figure 2.14: Revisited simulations of input match and K-factor for the non-
matched unit PA . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 2.15: Large signal power measurement setup . . . . . . . . . . . . . . 31
Figure 2.16: (a) Measured gain and output power of the combined PA at
39 GHz. (b) Measured PAE. Oscillations cause inaccurate mea-
surements for P < 17 dBm. . . . . . . . . . . . . . . . . . . . 32
in
Figure 3.1: (a) Simplified power amplifier and 2x2 antenna array system
block diagram. (b) Expanded system containing M chips to
achieve higher EIRP. . . . . . . . . . . . . . . . . . . . . . . . . 36
vii
Figure 3.2: Schematic of the 3-stack driver PA from [18]. All FETs have
45nm gate length, and all T-lines are grounded CPW lines . . . 38
Figure 3.3: Schematic of the 4-stack PA, used as primary driver and as each
half of the final pseudo-differential PA. All FETs have 45nm
gate length, and all T-lines are grounded CPW lines . . . . . . 40
Figure 3.4: (a) Simulated stability factor for the 4-stack PA for 3 cases: no
tuning; tuning with L2 only; and tuning with both L1 and L2.
(b) Simulated gain and output power for the PA at 45 GHz,
under the same tuning conditions. . . . . . . . . . . . . . . . . 42
Figure 3.5: Back-end metalization layers and CPW cross-section . . . . . . 43
Figure 3.6: (a) 3D view of the on-chip balun (part of the ground plane
was removed to show internal structure). (b) Simulated inser-
tion loss (IL), amplitude imbalance (∆A), and phase imbalance
(∆φ) of the integrated balun. . . . . . . . . . . . . . . . . . . . 44
Figure 3.7: Array power budget for 29 dBm total output power (based on
simulation). All values are in dBm . . . . . . . . . . . . . . . . 45
Figure 3.8: ESD architecture, R = 100 Ω . . . . . . . . . . . . . . . . . . . 45
Figure 3.9: Cross-section of the antenna array PCB. Antennas and CPW
lines are fabricated on L1. L2 is used for CPW ground shield,
while the antenna ground is on L4 . . . . . . . . . . . . . . . . 46
Figure 3.10: Geometry of the designed differential patch antenna (half patch
shown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 3.11: Simulated antenna array gain and directivity for the designed
arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 3.12: Phase of the input RF signal to the chip at different ribbon
bond dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 3.13: Degradation of the array directivity vs chip-to-chip phase error,
for a 2x8 array. A maximum phase error of 40o results in 1 dB
degradation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 3.14: Simulated antenna impedance (Z ) at 45 GHz at different
ANT
ribbon bond profile, and the PA load-pull. The locus of Z
ANT
from 40-50 GHz vs L and H is also shown for L : 475-
bw bw BW
775 µm and H : 200-400 µm . . . . . . . . . . . . . . . . . . 51
BW
Figure 3.15: (a) Die micrograph of the stand-alone 4-stack PA, with stan-
dard GSG pads for probing. (b) Die photo of the 2x2 chip
(2.5x4.5 mm2 including pads). . . . . . . . . . . . . . . . . . . . 54
Figure 3.16: Simulated and measured S-parameters of the balun structure.
Insertion loss (dB) of a single balun = 0.5*S . . . . . . . . . . 55
21
Figure 3.17: (a) Simulated and measured S-parameters of the 4-stack PA.
(b) Large signal gain and PAE vs output power of the PA at
45 GHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
viii
Figure 3.18: (a) Setup arrangement for chip probing. (b) Simulated and
measured S-parameters of the PA chip. Port-1 = Chip input
GSG, Port-2 = half of GSSG output (1/8 chip). . . . . . . . . . 57
Figure 3.19: PCB with 2.4 mm connectors assembly . . . . . . . . . . . . . . 58
Figure 3.20: (a) Measured aggregate output power of the array chip in class
AB and class A modes, at 45 GHz. (b) Measured overall PAE
at 45 GHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 3.21: (a) Antenna array assembly for the 2x2, with SMT capacitors
in close proximity for supply decoupling. (b) Antenna array
measurement setup. . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 3.22: Radiation patterns for the 2x2 array at 45 GHz . . . . . . . . . 62
Figure 3.23: (a) Measured EIRP along with the estimated total generated
power (P ) for the 2x2 array, at 45 GHz. P is computed
chip chip
based on an antenna array gain of 12 dB. (b) PAE of the PA
chip as inferred from the EIRP measurements, at 45 GHz. . . . 63
Figure 3.24: Maximum EIRP vs frequency for the 2x2 antenna array, when
biased in class AB mode . . . . . . . . . . . . . . . . . . . . . . 64
Figure 3.25: Antenna array assembly for the 2x8 . . . . . . . . . . . . . . . 65
Figure 3.26: Radiation patterns for the 2x8 array at 45 GHz . . . . . . . . . 67
Figure 3.27: (a) Measured EIRP along with the estimated total generated
power (P ) for the 2x8 array at 45 GHz. P is computed
chip chip
based on an antenna array gain of 17 dB. (b) PAE of the 2x8
array system at 45 GHz. . . . . . . . . . . . . . . . . . . . . . . 68
Figure 3.28: Maximum EIRP of the 2x8 array system in class AB mode vs
frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 3.29: Simplified schematic for stability analysis . . . . . . . . . . . . 72
Figure 4.1: (a) FET structure for the IBM 45nm SOI. (b) Back-end cross-
section of the process [42]. . . . . . . . . . . . . . . . . . . . . . 79
Figure 4.2: Simplified layout of the 32 µm FET . . . . . . . . . . . . . . . 82
Figure 4.3: (a) Thermal simulation of simplified 32 µm unit cell at 23 mW,
temperaturevaluesareinK. (b)Simulatedsurfacetemperature
rise, assuming uniform power source over the entire active area,
vs power sources in channel regions . . . . . . . . . . . . . . . . 83
Figure 4.4: Thermal simulation of simplified 32 µm unit cell at 23 mW,
with top dielectric included. Dotted arrows indicate various
heat conduction paths. Temperature values are in K . . . . . . 85
Figure 4.5: 3D model of the 32 µm unit cell . . . . . . . . . . . . . . . . . . 86
Figure 4.6: Cross section of the thermal distribution within the FET in-
cluding metal interconnects . . . . . . . . . . . . . . . . . . . . 87
ix