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About Design of High Speed Multiplier Using Modified Booth Algorithm With Hybrid Carry Look-Ahead Adder
This document summarizes a paper presented at the 2016 International Conference on Circuit, Power and Computing Technologies. The paper proposes a novel high-speed multiplier design that combines a modified Booth algorithm with a hybrid carry look-ahead adder. Specifically, it uses the modified Booth algorithm to reduce the number of partial products, and employs a new hybrid carry look-ahead adder structure to help control the overall delay of the multiplier and accumulator unit. Simulation results show the proposed multiplier and accumulator design has better performance than conventional designs in terms of reduced area overhead and critical path delay.
Detailed Information
| Author: | ['spkrishna4u7369'] |
|---|---|
| Publication Year: | 2017 |
| Pages: | 7 |
| Language: | English |
| Format: | |
| Price: | FREE |
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