Design of Energy-Efficient Application-Specific Instruction Set Processors (ASIPs)

255 Pages·2004·2.698 MB·English

by  Tilman Glökler, Heinrich Meyr

DESIGN OF ENERGY-EFFICIENT APPLICATION-
SPECIFIC INSTRUCTION SET PROCESSORS
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Design of Energy-Efficient
Application-Specific
Instruction Set Processors
by
Tilman Glökler
IBM Deutschland Entwicklung GmbH,
Böblingen, Germany
and
Heinrich Meyr
Integrated Signal Processing Systems,
Aachen University of Technology, Germany
KLUWER ACADEMIC PUBLISHERS
NEW YORK,BOSTON, DORDRECHT, LONDON, MOSCOW
eBookISBN: 1-4020-2540-8
Print ISBN: 1-4020-7730-0
©2004 Springer Science + Business Media, Inc.
Print ©2004 Kluwer Academic Publishers
Dordrecht
All rights reserved
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mechanical, recording, or otherwise, without written consent from the Publisher
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Contents
Foreword xi
Acknowledgments xii
About the Authors xiii
List of Figures xv
List of Tables xix
1 Introduction 1
2 Focusand Related Work 5
2.1 Focusof ThisWork . . . . . . . . . . . . . . . . . . . . 5
2.2 PreviousWork . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.1 ASIP DesignMethodologies . . . . . . . . . . 6
2.2.2 ASIP Case Studies . . . . . . . . . . . . . . . 10
2.2.3 Basic Low-PowerDesign Techniques . . . . . 11
2.2.4 Verification . . . . . . . . . . . . . . . . . . . 14
2.3 Differences toPreviousWork . . . . . . . . . . . . . . . 15
3 Efficient Low-Power Hardware Design 17
3.1 Metrics of the Implementation and the Hardware Design
Methodology . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.1 Characteristics of theImplementation . . . . . 18
3.1.2 Characteristics of theDesign Methodology . . 20
3.2 Basics ofLow-Energy Hardware Design . . . . . . . . . 22
3.2.1 Sources of CMOS Energy Consumption . . . . 23
3.2.2 Basic Principles of Lowering the Power Con-
sumption . . . . . . . . . . . . . . . . . . . . 26
vi Contents
3.2.3 Measuringand QuantifyingEnergy-Efficiency 28
3.3 TechniquestoReduce the EnergyConsumption . . . . . 32
3.3.1 Systemand Architecture Level . . . . . . . . . 33
3.3.2 Register Transferand LogicLevel . . . . . . . 36
3.3.3 PhysicalLevel . . . . . . . . . . . . . . . . . 40
3.4 ConcludingRemarks . . . . . . . . . . . . . . . . . . . 41
4 Application-Specific Processor Architectures 43
4.1 Definitionsof ASIP Related Terms . . . . . . . . . . . . 43
4.2 ASIP Applications . . . . . . . . . . . . . . . . . . . . . 46
4.3 ASIP Design Space . . . . . . . . . . . . . . . . . . . . 48
4.3.1 FunctionalUnits . . . . . . . . . . . . . . . . 51
4.3.2 Storage elements . . . . . . . . . . . . . . . . 52
4.3.3 Pipelining . . . . . . . . . . . . . . . . . . . . 53
4.3.4 InterconnectionStructure . . . . . . . . . . . . 55
4.3.5 ControlMechanisms . . . . . . . . . . . . . . 56
4.3.6 Storage Access . . . . . . . . . . . . . . . . . 58
4.3.7 InstructionCodingandInstructionFetchMech-
anisms . . . . . . . . . . . . . . . . . . . . . 59
4.3.8 Interface Mechanisms . . . . . . . . . . . . . 61
4.3.9 Tightly-CoupledASIP Accelerators . . . . . . 64
4.4 CriticalFactors for Energy-Efficient ASIPs . . . . . . . . 65
4.4.1 Timingand ComputationalPerformance . . . . 65
4.4.2 Energy Consumption . . . . . . . . . . . . . . 68
4.4.3 ImplementationArea . . . . . . . . . . . . . . 73
4.5 ConcludingRemarks . . . . . . . . . . . . . . . . . . . 74
Contents vii
5 The ASIP Design Flow 75
5.1 ExampleApplications . . . . . . . . . . . . . . . . . . . 76
5.2 ApplicationProfiling andPartitioning . . . . . . . . . . . 80
5.2.1 StimulusGeneration for ApplicationProfiling . 80
5.2.2 ApplicationProfiling . . . . . . . . . . . . . . 81
5.2.3 HW/SW Partitioning . . . . . . . . . . . . . . 87
5.2.4 ASIP Class Selection . . . . . . . . . . . . . . 89
5.3 CombinedASIP HW/SW Synthesisand Profiling . . . . 93
5.3.1 ASIP Interface Definition . . . . . . . . . . . 94
5.3.2 ASIP ISA Definition . . . . . . . . . . . . . . 96
5.3.3 Software Implementationand Tools . . . . . . 97
5.3.4 Hardware Implementationand Logic Synthesis 99
5.3.5 ImplementationProfiling and Worst Case Run-
timeAnalysis . . . . . . . . . . . . . . . . . . 100
5.3.6 IterativeASIP Optimization . . . . . . . . . . 102
5.3.7 Definitionof a tightlycoupledASIP Accelerator 109
5.4 Verification . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.5 ConcludingRemarks . . . . . . . . . . . . . . . . . . . 116
6 The ASIP Design Environment 117
6.1 TheLISA Language . . . . . . . . . . . . . . . . . . . . 117
6.2 TheLISA DesignEnvironment . . . . . . . . . . . . . . 123
6.3 Extensionstothe LISA DesignEnvironment . . . . . . . 125
6.3.1 InstructionEncodingand Decoder Generation . 125
6.3.1.1 Minimizationof theinstructionwidth 127
6.3.1.2 Minimizationof theToggleActivity 131
viii Contents
6.3.2 Semi-AutomaticTestCase Generation . . . . . 138
6.4 ConcludingRemarks . . . . . . . . . . . . . . . . . . . 143
7 Case Studies 145
7.1 Case Study I:DVB-T AcquisitionandTracking . . . . . 145
7.1.1 ApplicationProfiling and ASIP ClassSelection 147
7.1.2 IterativeInstructionSet Optimization . . . . . 149
7.1.2.1 Example1: Saturation . . . . . . . . 149
7.1.2.2 Example2: CORDIC . . . . . . . . 151
7.1.3 OverallEnergy OptimizationResults . . . . . 153
7.2 CaseStudyII:LinearAlgebraKernelsandEigenvalueDe-
composition . . . . . . . . . . . . . . . . . . . . . . . . 156
7.2.1 ImplementationI:OptimizedASIPwithAccel-
erator . . . . . . . . . . . . . . . . . . . . . . 157
7.2.2 Implementation II: Compiler-Programmed Pa-
rameterizable Core withAccelerator . . . . . . 161
7.2.3 EvaluationResults . . . . . . . . . . . . . . . 163
7.3 ConcludingRemarks . . . . . . . . . . . . . . . . . . . 165
8 Summary 167
A ASIP Development Using LISA 2.0 171
A.1 TheLISA 2.0Language . . . . . . . . . . . . . . . . . . 171
A.2 DesignSpace Exploration . . . . . . . . . . . . . . . . . 173
A.3 DesignImplementation . . . . . . . . . . . . . . . . . . 175
A.4 Software ToolsGeneration . . . . . . . . . . . . . . . . 177
A.4.1 CompilerGeneration . . . . . . . . . . . . . . 177
A.4.2 Assemblerand LinkerGeneration . . . . . . . 178
Contents ix
A.4.3 SimulatorGeneration . . . . . . . . . . . . . . 179
A.4.3.1 InterpretiveSimulation . . . . . . . 181
A.4.3.2 CompiledSimulation . . . . . . . . 181
A.4.3.3 Just-In-Time Cache Compiled Simu-
lation(JIT-CCS) . . . . . . . . . . . 181
A.5 SystemIntegration . . . . . . . . . . . . . . . . . . . . . 183
A.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 184
B Computational Kernels 185
B.1 TheCORDIC Algorithm . . . . . . . . . . . . . . . . . 185
B.2 FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . 187
B.3 TheFast Fourier Transformation . . . . . . . . . . . . . 188
B.4 Vector/MatrixOperations . . . . . . . . . . . . . . . . . 188
B.5 ComplexEVD usinga Jacobi-likeAlgorithm . . . . . . . 190
C ICOREInstruction Set Architecture 193
C.1 Processor Resources . . . . . . . . . . . . . . . . . . . . 193
C.2 PipelineOrganization . . . . . . . . . . . . . . . . . . . 193
C.3 InstructionSummary . . . . . . . . . . . . . . . . . . . 198
C.4 Exceptionsto theHiddenPipeline Model . . . . . . . . . 202
C.5 ICORE MemoryOrganizationand I/O Space . . . . . . . 203
C.6 InstructionCoding . . . . . . . . . . . . . . . . . . . . . 203
D Different ICORE Pipeline Organizations 205
E ICOREHDL Description Templates 207
E.1 Generic RegisterFile Entity . . . . . . . . . . . . . . . . 207
E.2 Generic Bit-ManipulationUnit . . . . . . . . . . . . . . 209