Design of an Operational Amplifier for High Performance Pipelined ADCs in 65nm CMOS Author

105 Pages·2012·2.23 MB·English

Design of an Operational Amplifier for High Performance
Pipelined ADCs in 65nm CMOS
Master thesis performed in Electronic Devices
Author: Sima Payami

Report number: LiTH-ISY-EX--12/4571--SE
Linköping, June 2012

Design of an Operational Amplifier for High Performance
Pipelined ADCs in 65nm CMOS
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Master thesis Performed in Electronic Devices
at Linköping Institute of Technology
by Sima Payami

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LiTH-ISY-EX--12/4571--SE

Supervisor: Professor Atila Alvandpour

Examiner: Professor Atila Alvandpour

Linköping, June 2012

Presentation Date Department and Division

8th June 2012 Department of Electrical Engineering
Publishing Date (Electronic version) Electronic Devices

25th June 2012

Language Type of Publication
ISBN (Licentiate thesis)

 English Licentiate thesis

ISRN: LiTH-ISY-EX--12/4571--SE
Other (specify below)  Degree thesis

Thesis C-level Title of series (Licentiate thesis)
Thesis D-level
Report Series number/ISSN (Licentiate thesis)
Number of Pages Other (specify below)
87 pages

URL, Electronic Version
http://urn.kb.se/resolve?urn= urn:nbn:se:liu:diva-78930

Publication Title

Design of an Operational Amplifier for High Performance Pipelined ADCs in 65nm CMOS

Author(s)
Sima Payami

Abstract
In this work, a fully differential Operational Amplifier (OpAmp) with high Gain-Bandwidth (GBW), high
linearity and Signal-to-Noise ratio (SNR) has been designed in 65nm CMOS technology with 1.1v supply
voltage. The performance of the OpAmp is evaluated using Cadence and Matlab simulations and it satisfies
the stringent requirements on the amplifier to be used in a 12-bit pipelined ADC. The open-loop DC-gain of
the OpAmp is 72.35 dB with unity-frequency of 4.077 GHz. Phase-Margin (PM) of the amplifier is equal to
76 degree. Applying maximum input swing to the amplifier, it settles within 0.5 LSB error of its final value
in less than 4.5 ns. SNR value of the OpAmp is calculated for different input frequencies and amplitudes
and it stays above 100 dB for frequencies up to 320MHz.
The main focus in this work is the OpAmp design to meet the requirements needed for the 12-bit pipelined
ADC. The OpAmp provides enough closed-loop bandwidth to accommodate a high speed ADC (around
300MSPS) with very low gain error to match the accuracy of the 12-bit resolution ADC. The amplifier is
placed in a pipelined ADC with 2.5 bit-per-stage (bps) architecture to check for its functionality.
Considering only the errors introduced to the ADC by the OpAmp, the Effective Number of Bits (ENOB)
stays higher than 11 bit and the SNR is verified to be higher than 72 dB for sampling frequencies up to 320
MHz.

Keywords
Pipelined, ADC, OpAmp, Gain Boosting, CMFB, 2.5bps architecture, Flash, MDAC

Abstract

In this work, a fully differential Operational Amplifier (OpAmp) with high Gain-
Bandwidth (GBW), high linearity and Signal-to-Noise ratio (SNR) has been
designed in 65nm CMOS technology with 1.1v supply voltage. The performance of
the OpAmp is evaluated using Cadence and Matlab simulations and it satisfies the
stringent requirements on the amplifier to be used in a 12-bit pipelined ADC. The
open-loop DC-gain of the OpAmp is 72.35 dB with unity-frequency of 4.077 GHz.
Phase-Margin (PM) of the amplifier is equal to 76 degree. Applying maximum
input swing to the amplifier, it settles within 0.5 LSB error of its final value in less
than 4.5 ns. SNR value of the OpAmp is calculated for different input frequencies
and amplitudes and it stays above 100 dB for frequencies up to 320MHz.
The main focus in this work is the OpAmp design to meet the requirements needed
for the 12-bit pipelined ADC. The OpAmp provides enough closed-loop bandwidth
to accommodate a high speed ADC (around 300MSPS) with very low gain error to
match the accuracy of the 12-bit resolution ADC. The amplifier is placed in a
pipelined ADC with 2.5 bit-per-stage (bps) architecture to check for its
functionality. Considering only the errors introduced to the ADC by the OpAmp,
the Effective Number of Bits (ENOB) stays higher than 11 bit and the SNR is
verified to be higher than 72 dB for sampling frequencies up to 320 MHz.

Keywords: Pipelined, ADC, OpAmp, Gain Boosting, CMFB, 2.5bps architecture,
Flash, MDAC

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Acknowledgement

I would like to express my gratitude and appreciation to all the people who have
helped and supported me in the process of this thesis. Without their help and
support, I would not be able to reach this level of satisfaction with what I have
learnt and accomplished during my master thesis.
First of all I would like to thank my supervisor Professor Atila Alvandpour for his
guidance, valuable ideas and all the insightful discussions. Thank you for the
wonderful experience.
Secondly, I am thankful to Amin Ojani, Mostafa Savadi, Timmy Sundstrsom, Ali
Fazli, Ameya Bhide, and Daniel Svärd, former and current Ph.D. students in
Electronic Device division, for their help. I have benefited from all the useful
discussions with them. All the beneficial suggestions I have received from them
helped me to improve my work.
Furthermore, I would like to thank Associate Professor Jacob Wikner and Dr.
Christer Jansson for their help which was given most kindly whenever I needed.
At the end I want to thank my beloved family and friends for their support and
understanding during my studies. I am grateful to them who have enriched my life,
encouraged and helped me to overcome all difficulties.

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