Design of a Programmable Switched-Capacitor Analog FIR Filter

131 Pages·2000·5.6 MB·English

Design of a Programmable
Switched-Capacitor Analog FIR Filter
Cameron Lacy
A thesis submitted in confonnity with the requirements
for the degree of Master of Apptied Science
Graduate Department of Electricd Engineering
University of Toronto
O Copyright Cameron B. Lacy, 1999
1+1 National Libraiy Bibliothèque nationale
,cana, du Canada
Acquisitions and Acquisitions et
Bibliographie Services services bibliographiques
395 Wellington Street 395. rw Wdliigtm
OtîawaON KlA ON4 OctawaON K f A W
canada canada
The author has granted a non- L'auteur a accordé une iicence non
exclusive licence allowing the exclusive permettant a la
National Library of Canada to Bibliothèque nationale du Canada de
reproduce, loan, distnbute or sell reproduire, prêter, distribuer ou
copies of this thesis in microfom, vendre des copies de cette thèse sous
paper or electronic formats. la forme de microfiche/film, de
reproduction sur papier ou sur format
électronique.
The author retains ownership of the L'auteur conserve la propriété du
copyright in this thesis. Neither the droit d'auteur qui protège cette thèse.
thesis nor substantial extracts fkom it Ni la thèse ai des extraits substantiels
may be printed or otherwïse de celle-ci ne doivent être imprimés
reproduced without the author's ou autrement reproduits sans son
permission. autorisation.
Design of a Programmable
Switched-Capacitor Analog FIR Filter
Cameron B. Lacy
Department of Electrical and Cornputer Engineering
University of Toronto
Degree of Master of Applied Science, 1999
Abstract
The use of an analog adaptive filter can offer benefits over a digital adaptive filter in applications that
require high-speed, low-power, and a moderate degree of Linearity. An adaptive digital FIR filter will typ-
ically be implemented as a finite impulse response filter using a pipelined tapped delay line with program-
mable tap coefficients. When an analog adaptive filter is constructed, a parallel tapped delay line is used.
A programmable andog FIR will typically use buffered sarnple-and-hold blocks for the analog deIay line
and tnnsconductors to implement the MDACs used for the tap coefficient multiplication. The research
focusses on a more passive approach to the circuit realization. An entirely voltage-mode, switched-capac-
itor implementation is presented. A seven tap adaptive analog FIR Nter using the passive architecture is
realized in an area of 1. 44mm2.T he fabricated chip has a power dissipation of 104mW using a sampling
frequency of 200MHz and a power supply of 3.3V.
Acknowledgements
1 would tike to thank my advisor, David Johns, for his guidance and support- Without his ideas and
insights, this wotk would not have ken possible.
1 would aiso like to thank my thesis CO-advisor,A del Sedra, for sponsoring me and providing encourage-
ment. Afso thanks to Diane for taking the time to fit me into a busy schedule,
Thanks to the gang in EA 104 for providing a stimula~wgo rlang environment Best wishes to Anas,
Angus, Amir, Bahram, Dickson, James, Khoman, Raj, Sebastian, Steve, Takis, and Vasil. Special thanks to
Steve for help with the implernentation of a cyciic anaiog delay hue.
Thanks to the University of Toronto and to NSERC for their financial support To the Canadian Microelec-
tronics Corporation for theù grant of fabrication and for their quick turn-around.
Most of dl, 1 would like to thank Kate for putting up with me and for the support and encouragement that
you provided for the pst two years.
Table of Contents
.
CHAPTER 1 Introduction
... .n..-.tHH....-.......-........-rm-.......Hn...........HI.....u.....~...HI...-.n....
1.2 Applications 1
1.2.1 Channel Equalizer. ...................................................................................................... 1
.......................................................................................................
1-2-2E cho Cancellation 2
..... . ..........-
1.3 State of the Art ....................... 3
. .
1.3.1 Adaptive Filtering for a Disk Drive Read Channel .................................................... 3
.". ...-
1.5 References .........-....... .n............H.n........................................6
..-..."...O"..
.
CHAPTER 2 Background
..... ....
2.1 Generic Digital FIR Filter Architecture .....-.......n.............W.n..............~.....H.......7.. ......
2.1.1 Direct Form FIR Architecture ..................................................................... .... 7
2.1.2 Transpose FiR Architecture ........................................................................................ 8
. . . , . . . . . . . . ....."., .. ............... . .
2.2 Andog Delay Line 8
2.2.1 Pipelined Analog Delay Line ................................................................................... 8
2.2.2 Parallel Analog Delay Line ................................................. .. ................ 9
2.2.3 Parallel Anaiog Delay Line with Extended Input Acquisition Tirne ........................ 11
....-..
2.3 Generic AdogF IR Fiter Architech rm. n . ,
2.3.1 Rotating Switch Matrix Architecture .................................................................... 12
2.3.2 Coefficient Shuffling Architecture ........................................................................... 12
2.3.3 Summary of Switch Mauix vs .C oefficient Shuffling ......................................*.......1 4
..... .... ....... ......... .................- ... ........-...
2.4 Implementation of Parailel Anaiog Deiay Line .-1 5
2.4.1 List of Papers ............................................................................................................ (5
2.4.2 Summary ................................................................................................................... 16
........ . ....... . ..,....... ............ ........... ..... ........
2.5 Other Architectures .... .................................. 18
2.5.1 Pipelined Analog Delay Line ................................................................................. 18
25.2 Current Mode Technique .......................................................................................... 18
26 Chapter Summary. .......... . .. .... ...........n.............................., ...............,... .................... .. 19
.................. ...... . ...............
27 References ................................................................... U)
..
.
CHAPTER 3 Architecture
3.1 Pmposed Architecaire ~ ~ ~ ~ ~ ~ U I n ~ ~ ~ ~ ~ ~ n n ~ ~ ~ ~ ~ U I I ~ W . u I I H I I H ~ ~ n ~ ~ ~ ~ ~ ~ ~ ~ U ~ ~ H H H U ~ W ~ W W I I I U
3.1.1 Parallel AnaIog Delay Line ...............................................
3.1.2 Tap Gain Stage (MDAC).. ........................................................................................ 30
3.1.3 Sumrning Stage. ........................................................................................................ 34
...................................................................................................................
3.1.4 Summary 35
-.
3.2 Fiied Pattern Noise... ............. H....~...mN.-....m+r.-..)......~..................nn..........3..... 6
3.2.1 Signal Dependent FPN ............................................................................................. 36
3.2.2 Signal Independent FPN ........................................................................................... 39
., ... ......
4.2 System Levei Design " .....,.......n..-.....-.......nH.......*..U.oWW...*.........H... 43
4.rn~ 1. Packaging. ................................................................................................................. 43
4.2.2 Hoorplan (Area Allocation) ..................................................................................... 45
4.2.3 Power Consurnption Ailocation. ............................................................................... 46
4.2.4 Switched Capacitor Architecture Considerations. .................................................... 46
4.2.5 Distortion .................................................................................................................. 47
4.2.6 Noise ...................................................................................................................... 47
4.2.7 Fixed Pattern Noise .................................................................................................. 48
4.2.8 Chip Testability ......................................................................................................... 49
. . . . . . . . , . . . ..... .
4.3 Adog C*ir cuihy -.....*.*.**,*...
.............................................................................................
4.3.1 Oparnp Bias Generator 50
..............................................................................................................
4.3.2 Input Buffer 52
4.3.3 Pdlel Analog Delay Line ........................ .... ...................................................... 54
4.3.4 MDACs ..................................................................................................................... 59
............................................................................................................
4.35 Output Driver 61
4.3.6 Output Summing Stage ............................................................................................. 63
...
4.4 Digital CiMitry ....I...............n..................~.....*n.~.N..Hn.......*.............................-.~O..7.0.. ....
4.4.1 Clock Generator ........................................................................................................ 70
........................................................................................
4.4.2 Coefficient Loading Logic 70
4.4.3 Coefficient Shuffling Logic ..................................... ... .............................................. 72
........... .....~..n........H...~.-............-...C.I....W......~......... ............
4.5 O v e dS ystem ...............- 74
................................................................................
45.1 Summary of Power Dissipation 74
4.5.2 Summary of Noise .................................................................................................... 74
.............................................................................................
45.3 Summary of Distortion 76
4.7 Chapter Suma>pm. .... ...... .......*-.............. .... .......W.CI.~...-.....................H...n..........7..8.. .....
...
5.1 Measur e-m-e..n.t T-e.s&tm k p...-..... 8.-0
5.2 Bi Circuit ..........n....n.mn.-..... ..-.- ....-u......C...CCC....................8.1. .
... .. ..- .......... .. ........ .- ...-...... -".. ....... ... -- ................
5.3 Frequency Spectrum " ................. 83
5.3. I Characterizahon of Distomon .................................................................................. 83
5.3.2 Gain vs .C oefficient Relationship ............................................................................ 8 8
-
5.4 TkllSfer Function .....m.UI...---...........-......n-.....n.....-.........H....w %
5.4.1 Single Enabled Tap ................................................................................................. 93
.............................................................................
5.4.2 Lowpass. Highpass. Bandpass 96
.... ..... . .......... ....-.............. ............ ..... ...... .. ..................... .. ........................
55P ower Coasumption 9T
..... .. ......... .. ...... ..
5.6 Chapter Summary .........U..n.........n................n.................1..0.1.
5.7 References .-...................W........... .. . ....u-.......... 103
u UII
.
CIWETER 6 Conclusion and Future Research
.
APPENDM A Derivation: CDS Amplifier Transfer Function
.
APPENDIX B Derivation: Fixed Pattern Noise
...... ................... ..... ...............................
B.l Signai Dependent Fied Pattern Noise il2
B .1 .1 Output Spectrum .................................................................................................... 112
B .1 .2 Limit on Path Gain Deviation ................................................................................ 116
..--.............. ....O..... .....-.....O....... .......
B 3S ignai Independent Fied Pattern Noise il8
B.2.1 Resulting Output Specuum ................................................................................... 120
............*...... .. ....................................................
B.2.2 Limit on Patb Offset Deviation 12i
List of Figures
.
CHAPTER 1 Introduction
..............................................................................................................
Figure 1: Channel Equalizer 2
Figure 2: Echo Cancellation ......... . ..................................................................................................... 3
Figure 3: Disk Drive Read Channel ................................... ... ........................................................ ..... 3
.
CHAPTER 2 Background
Figure 4: Digitai FIR Architecture. .................................................................................................
Figure 5: Delay Lme Architecture ................................................................................................... IO
Figure 6: Generic Analog Architecture with a Rotating Switch Matrix ......................................... 13
Figure 7: Generic Analog Architecture with Coefficient Shuffling. ................................................ 14
.
CHAPTER 3 Architecture
Figure 8: Proposed Passive implementation .................................................................................... 23
Figure 9: Regular Capacitor Matrix ................................................................................................. 24
Figure 10: ReguIar Capacitor Matrïx Progression ........................................................................... 25
Figure 11 : Cyclic Matrix ............... .... ..................................................................................... -27
..............................................................................................
Figure 12: Cyclic Mauix Progression 28
Figure 13: Layout of Circular Capacitor Arrangement. ................................................................... 29
Figure 14: Charge Sharing from Sample-and-Hold to MDAC ........................................................ 30
Figure 15: Ideal 2C-C Ladder .................... .. ...............................................................................*3. 1
Figure 16: Non-Ideal 2C-C Ladder ElemenL ................................................................................... 32
Figure 17: Plot of Coefficients vs .G ain ........................................................................................... 33
Figure 18: CDS Opamp Suitable for use with Capacitor Ladder MDAC ....................................... 34
Figure 19: FPN .i deal Output Specûum ......................................................................................... 37
Figure 20: FPN .N on-ideal Output Spectrurn .................................................................................3 8
.
CHAPTER 4 Design
Figure 21: Overall System Block Diagram. ..................................................................................... 43
Figure 22: Chip Floorplan ................................................................................................................ 45
Figure 23: Systcm Noise Analysis ................................................................................................... 47
Figure 24: Relationship Between Gain Misrnatch and Capacitor Mismatch ................................... 49
Figure 25: Constant Transconductance B ias Circuit Schematic ..................................................... 51
Figure 26: Input BufFer Schematic. .................................................................................................. 53
Figure 27: BIock Diagram of Seven Tap Passive Analog Delay Line ............................................. 55
Figure 28: Output Routing Algorithm ................... .. .................................................................... 56
Figure 29: Output Routing Logic for a Single Row ......................................................................... 56
..............................................................................
Figure 30: Input Capacitor Matrix S/H Element 57
Figure 3 1: Analog Delay Line .O utput for an input Sinusoid ........................................................ 59
Figure 32: Modified System Block Diagram ................................................................................... 60
Figure 33: Modified MDAC Structure (7-bit) ................................................................................. 61
Figure 34: Output Driver Schematic ...................... ... ................................................................. 62
Figure 35: Structure of the Output SumMng CDS Opamp ............................................................. 64
Figure 36: Cumnt Mirmr Opamp Schematic. .......... .. ................................................................. 67
vii
Figure 37: Common Mode Feedback Circuit .................................................................................. 68
Figure 38: CDS Amplifier Output Senling Characteristic. .............................................................. 69
Figure 39: Clock Generation Circuitry ............................................................................................ 71
Figure 40: Simulation of Clock Generation Circuitry .................................... ... ............................. 72
Figure 41: Coefficient Loading Logic. ............................................................................................. 73
Figure 42: Coefficient Loadin ..g..... ..S.......e.....q.....u......e.....n.....c......e.... 73
Figure 43: Coefficient Shuming Logic ...... ................ . ............................................................ 74
Figure 44- Simulation of Coeficient Logic ...................,,...................................................... .......... 75
Figure 45: Plot of Circuit Layout .................................................................................................... -77
.
CHAPTER 5 Measurement & Analysis
Fi- 46: Test Cucuit .................... .. ............................................................................................ 81
Figure 47: Simulation Plot of Bias Circuit Loop Gain .................................................................... 83
Figure 48: Output Spectnim .1 0 MHz Sampling .N o Taps Enabled .......................................... 85
Figure 49: Output Spectrum .1 0 MHz Sampling .S ingle Tap .N o Input-. .................................... 85
Figure 50 Output Spectrum .1 0 MHz Sampling .S ingle Tap .1 MHz Input ...............................8 6
Figure 5 1 : Output Spectm .1 0 MHz Sampling .S ingle Tap .2 MHz Input ............................ -86
Figure 52: Output Spectrum .1 0 MHz Sampling .S ingle Tap .3 MHz Input ............................... 87
Figure 53: Output Spectrum .1 0 MHz Sarnpling .S ingle Tap .4 MHz Input ............................... 87
Figure 54: Cause of Memory Present in System. ............................................................................. 88
Figure 55: Simulated Response of Analog Delay Line Output with Redundant Switch ................. 89
Figure 56: Simulated Response of Analog Delay Line Output with Switch Removed ................... 89
Figure 57: Output Spectrum .2 50 MHz Sampling .S ingle Tap .N o Input. .................................. 90
Figure 58: Output Spectnim .2 50 MHz Sampling .S ingle Tap .1 0 MHz Input ........................... 90
Figure 59: Output Spectnim .2 50 MHz Sampling .S ingle Tap .2 0 MHz Input .......................... -91
Figure 60: Output Spectrurn .2 50 MHz Sampling .S ingle Tap .4 0 MHz Input ........................... 91
Figure 61: PIot of Tap Gain .............................................................................................................. 92
Figure 62: Measured Address Dependency in Tram fer Function ................................................... 94
Figure 63: Plots of (l+A)z-x ............................................................................................................ 95
Figure 64: Derived Address Dependency in Transfer Function ...................................................... %
Figure 65: Corrected Tap Tram fer Functions ................................................................................. -97
Figure 66: Transfer Function .1 0 MHz Sampling .L owpass (l+z-1). ........................................ 98
Figure 67: Transfer Function .2 50 MHz Sampling .L owpass (l+z-1).. ........................................ 98
Figure 68: Transfer Function .1 0 MHz Sampling .H ighpass (1-2-1).. .......................................... 99
Figure 69: Tram fer Function .2 50 MHz Sampling .H ighpass (1 -2-1 ) .......................................... 99
Figure 70: Transfer Function .1 0 MHz SampIing .B andpass (1-2-2) .......................................... 100
Figure 71: Transfer Function .2 50 MHz Sampiing .B andpass (1-2-2.).. ..................................... 100
Figure 72: Power Consumption vs . Operating Frequency ............................................................. 101
.
APPENDM A Derivation: CDS Amplifier 'Ikansfer Function
Figure 73: CDS Amplifier. ........., .. ............................................................................................. 106
Figure 74: CDS oparnp state at the end of each clock phase ... ............................ .......................... 107
Figure 75: Example CDS Opamp Tramfer Function .................................................................... Ill
.
APPENDM B Derivation: Fixed Pattern Noise
Figure 76: MATLAB Code for Distortion Simulation ................................................................... 119
Figure 77: Sample Output Plot Showing Signal Dependent Fixed Pattern Noise Distortion. ....... 120
viii
CHAPTER Introduction
1.1 Adaptive Filters
Adaptive filters are used to improve the operation of many high speed communications systerns- They per-
form many ta& such as the removal of intersymbol interference and echo cancellation. ALI of these tasks
are typically accomplished using a programmable digital finite impulse response (FIR) filter. Often, an
FIR filter is used due to its simple structure and because it simplifies the adaptation algorithm. A digital
implernentation of the filter can use a large arnount of power particularly if the speed and accuracy require-
ments are high. As wilt be shown, the use of an analog FIR filter in place of the digital FIR filter can help
reduce this requirement.
1.2 Applications
Analog adaptive filters can be used to perform many of the tasks usudly assigned to digital adaptive filters.
These analog filters can be used to reduce intersymbot interference (ISI) in a channel equalizer or in an
echo canceller to remove of unwanted signals present in a receive path.
1.2.1 Channel Equalizer
In a digital receiver, because equalization is typicdy performed in the digital domain, îhere wiil be an ana-
Iog-to-digital converter (ADC) before the equalizer. The use of a programmable analog FIR filter allows