Design of a 16-bit 50-kHz Low-Power SC Delta-Sigma Modulator for ADC in 0.18um CMOS ...

88 Pages·2016·3.6 MB·English

by  Jose Cisneros Fernàndez

UNIVERSITAT POLITÈCNICA DE CATALUNYA
Design of a 16-bit 50-kHz Low-Power
SC Delta-Sigma Modulator for ADC
in 0.18um CMOS Technology
MASTER THESIS
IMB-CNMSupervisors:
MicheleDei
Author:
FranciscoSerraGraells
JoseCisnerosFernàndez
UPCco-advisor:
XavierAragonèsCervera
Athesissubmittedinfulfillmentoftherequirements
forthedegreeofMasterofElectronicEngineering
inthe
ETSETB
EscolaTècnicaSuperiord’EnginyeriadeTelecomunicacióde
Barcelona
July10,2016
ii
UNIVERSITATPOLITÈCNICADECATALUNYA
ETSETB
MasterofElectronicEngineering
Designofa16-bit50-kHzLow-PowerSCDelta-SigmaModulatorfor
ADCin0.18umCMOSTechnology
JoseCisnerosFernàndez
Abstract
A general purpose 16 Bits Σ-∆ modulator ADC for double precision
audio50kHzbandwidth,targetedforLow-poweroperation,involvingno
additional digital circuit compensation, no bootstrapping techniques and
resistor-less topologies, and relaying on Switched Capacitor Σ-∆ modula-
tortopologiesforrobustoperationandinsensitivitytoprocessandtemper-
aturevariations,ispresentedinthiswork.
Designed in a commercial 180 nm technology, the whole circuit static
current is calculated in 620 µA with a nominal voltage supply of 1.8 V,
performing a Schreier FOM of 174.16 dB. This outstanding state-of-the-art
forseen FOM is achieved by the use of architectural and circuital Low-
power techniques. At the architectural level a single loop Low-distortion
topologywiththeoptimumorderandcoefficientshavebeenchosen,while
atcircuitlevelverynovelOTAbasedonVariableMirrorAmplifiersallows
anefficientClass-ABoperation.
Specially optimized switched variable mirror amplifiers with a novel
design methodology based on Bottom-up approach, allows faster design
stages ensuring feasable circuit performance at architectural level without
the need of large iterative simulations of the complete SC Σ-∆ modula-
tor. Simulationresultsconfirmsthecompleteoptimizationprocessandthe
metionedadvantageswithrespecttothetradicionalapproach.
KEY WORDS- 16 Bits, 50 kHz, Low-Power, Low-Distortion, No boostrapping,
SwitchedCapacitorΣ-∆modulator.
iii
Acknowledgements
Iowemygratitudetoallthosewhocontributedinsomewayinthere-
alizationofthismasterthesis.
Firstly, I would like to thank Dr. Francisco Serra Graells and Dr. Lluis
Teres for the oportunity to develop my master thesis in the ICAS group at
IMB-CNM.
This Thesis would not have been possible without the guidance and the
help of Dr.Michele Dei and Dr. Francisco Serra, from which I’m thankful
fortheirpatience,motivation,andknowhow. Theirguidancehelpedmein
allthetimeofdevelopmentandwritingofthisthesis.
I would like to express my sincere gratitude to my advisor Dr. Xavier
Aragones, which gives me the opportunity and the time I need to learn
fromthisworldofelectronics,withoutexpectinganythinginreturn.
IwouldliketoexpressmydeepestthankstoJoanAymerich,forbeingpart
of this journey through the micro-electronics world and provide support
and advice when needed. With no doubt its a pleasure to find people like
you.
LastbutnottheleastIwouldliketothankmyparentsandbrotherfortheir
unending support and encouragement. Without their support this work
wouldnothavebeenpossible.
iv
Contents
Abstract ii
Acknowledgements iii
1 Introduction 1
1.1 ADCFundamentals . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 ADCarchitectures . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 State-of-the-artADCs . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Σ-∆ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4.1 Σ-∆ModulationBasics . . . . . . . . . . . . . . . . . 7
1.4.2 CTandDTΣ-∆Modulation . . . . . . . . . . . . . . 9
1.4.3 ClassificationofΣ-∆Modulators . . . . . . . . . . . 10
1.5 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.6 Designmethodologies . . . . . . . . . . . . . . . . . . . . . . 12
1.7 StructureoftheWork . . . . . . . . . . . . . . . . . . . . . . . 16
2 Measurements 17
2.1 Σ-∆performancemetrics . . . . . . . . . . . . . . . . . . . . 17
2.2 Σ-∆ModulatorexpectedPerformance . . . . . . . . . . . . . 19
2.3 Σ-∆TestVehicle. . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.1 TestVehicleEquipment . . . . . . . . . . . . . . . . . 20
2.3.2 TestVehicleBoard . . . . . . . . . . . . . . . . . . . . 21
2.3.3 TestVehicleSoftware . . . . . . . . . . . . . . . . . . . 22
2.4 Σ-∆ModulatorMeasurements . . . . . . . . . . . . . . . . . 23
2.4.1 MeasurementProcedure . . . . . . . . . . . . . . . . . 23
2.5 MeasurementResults . . . . . . . . . . . . . . . . . . . . . . . 23
2.6 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3 HighlevelΣ-∆modelling 26
3.1 Σ-∆modulatortopologies . . . . . . . . . . . . . . . . . . . . 27
3.1.1 DistributedfeedbackΣ-∆modulator . . . . . . . . . 27
3.1.2 FeedforwardΣ-∆modulator . . . . . . . . . . . . . . 30
3.2 Σ-∆ModulatorTopologyElection . . . . . . . . . . . . . . . 32
3.3 CoefficientOptimization . . . . . . . . . . . . . . . . . . . . . 34
3.4 Mismatchrobustnesstest. . . . . . . . . . . . . . . . . . . . . 37
3.5 Settlingrobustnesstest . . . . . . . . . . . . . . . . . . . . . . 39
3.6 Clockjitterrobustnesstest . . . . . . . . . . . . . . . . . . . . 40
3.7 Referencenoiserobustnesstest . . . . . . . . . . . . . . . . . 41
3.8 Thermalnoise . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4 Circuitleveldesign 44
4.1 SwitchedCapacitorΣ-∆Modulator . . . . . . . . . . . . . . 44
4.2 Modulatorbuildingblocks . . . . . . . . . . . . . . . . . . . . 50
4.2.1 PhaseSplitter . . . . . . . . . . . . . . . . . . . . . . . 50
v
4.2.2 Single-bitQuantizer . . . . . . . . . . . . . . . . . . . 51
4.2.3 SwitchedVariable-MirrorAmplifiers . . . . . . . . . 52
4.2.3.1 SwitchedVariable-MirrorAmplifiersprinci-
pleofoperation . . . . . . . . . . . . . . . . 53
4.2.3.2 SwitchedVariable-MirrorTypes . . . . . . . 54
4.2.3.3 SwitchedVariable-MirrorSCimplementation 56
5 Circuitoptimizationandsimulationresults 58
5.1 SimulationTestbench . . . . . . . . . . . . . . . . . . . . . . . 58
5.2 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.2.1 Switchesoptimizationprocess . . . . . . . . . . . . . 62
5.3 SwitchedVariableMirrorAmplifier . . . . . . . . . . . . . . 63
5.3.1 Designspaceandalternatives . . . . . . . . . . . . . . 63
5.3.2 Slewrateandlinearrelaxation . . . . . . . . . . . . . 65
5.3.3 SVMAType1Optimization . . . . . . . . . . . . . . . 66
5.3.4 SVMAType2Optimization . . . . . . . . . . . . . . . 68
5.3.5 2nd and3rd SVMAstages . . . . . . . . . . . . . . . . 71
5.4 SCΣ-∆Melectricalsimulations . . . . . . . . . . . . . . . . . 71
6 Conclusions 74
6.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.2 Futurework . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
References 76
vi
List of Figures
1.1 ADC basic block diagram and Analog-to-Digital conversion
process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 (A) 6-level quantizer characteristic and its quantization er-
ror, (B) equivalence of the quantizer block diagram with its
simplifiedlinearmodelaccountingfortheinjectionofauni-
formlydistributedwhitenoise. . . . . . . . . . . . . . . . . . 3
1.3 Murmann survey of ADC performance: representation on
theENOBversussignalbandwidthplane. . . . . . . . . . . . 5
1.4 Murmann survey of ADC performance: representation on
theenergy-per-conversionversustheENOB. . . . . . . . . . 6
1.5 In-bandnoisepowerrepresentationsinthreedifferentcases:
Nyquist-rateADC,oversampledADCandoversampledwith
noiseshapingADC. . . . . . . . . . . . . . . . . . . . . . . . . 8
1.6 BasicsingleloopΣ-∆Modulatorblockdiagram. . . . . . . . 8
1.7 Discretetime(A)andContinuoustime(B)Σ-∆modulators
blockdiagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.8 Design flow diagram adopted in this work. Design tasks
havebeenmappedtotheirrespectivedesignenvironment. . 13
2.1 Typical Σ-∆ Modulator power spectral density with perfor-
mancemetrics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 Graphicalrepresentationofthemostimportantperformance
metricsofΣ-∆ADC. . . . . . . . . . . . . . . . . . . . . . . . 19
2.3 TestvehicleboardoftheΣ-∆ADCof[32]. . . . . . . . . . . 21
2.4 Σ-∆ModulatorPSDmeasurementoftheΣ-∆ADCof[32]. 22
3.1 DesignflowofHighlevelmodulatorimplementation. . . . . 27
3.2 L-thorderdistributedfeedbackΣ-∆Modulator. . . . . . . . 28
3.3 2nd orderdistributedfeedbackΣ-∆Modulator. . . . . . . . . 28
3.4 Transient simulation and signal distortion at integrator out-
putsfora2nd orderdistributedfeedbackΣ-∆modulator. . . 30
3.5 L-thorderFeedforwardΣ-∆Modulator. . . . . . . . . . . . 30
3.6 2nd orderFeedforwardΣ-∆Modulator. . . . . . . . . . . . . 31
3.7 Transient simulation and signal distortion at integrator out-
putsfora2nd orderfeedforwardΣ-∆modulator.. . . . . . . 32
3.8 Block diagram of the 3rd order feedforward Σ-∆ modulator
developedinthiswork. . . . . . . . . . . . . . . . . . . . . . 34
3.9 Transientsimulationsandstatevariablesdistributionfortwo
differentcandidatesofthegridsearchalgorithm. . . . . . . . 36
3.10 High level simulation results of 3rd order Σ-∆ modulator
modelofthiswork. . . . . . . . . . . . . . . . . . . . . . . . . 37
3.11 Mismatchcoefficienttestresults. . . . . . . . . . . . . . . . . 38
3.12 SNDRdegradationasfunctionoftheintegratorsettlingerror. 39
vii
3.13 Graphical representation of a non-uniform sampling of a si-
nusoidalsignalduetoclockjitter. . . . . . . . . . . . . . . . . 40
3.14 SNDRdegradationasfunctionofJitter. . . . . . . . . . . . . 41
3.15 Referencenoisetestresults. . . . . . . . . . . . . . . . . . . . 42
3.16 High level PSD-spectrum with (Grey) and without (Black)
thermalnoise. . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.1 InterleavedoperationofswitchedOpAmpsina3rd orderΣ-
∆ Modulator. This implementation modifies the loop trans-
ferfunctioninawaythatmakethemodulatordysfunctional.
Itisshownhereforillustrationpurposes. . . . . . . . . . . . 45
4.2 3rd order Σ-∆M SC based on switched OpAmps. Here the
switched OpAmps blocks are labelled as SVMA accounting
fortheswitchedvariablemirroramplifiers. . . . . . . . . . . 46
4.3 Rearrangement of half delays in a cascade of two half delay
integrators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.4 Σ-∆MSC-switchedOpAmpschematicduringφ . . . . . . 48
1−2
4.5 Σ-∆MSC-switchedOpAmpschematicduringφ . . . . . . 49
3−4
4.6 Σ-∆Mphasegenerator. . . . . . . . . . . . . . . . . . . . . . 50
4.7 Σ-∆Moperationchronogram. . . . . . . . . . . . . . . . . . . 51
4.8 Σ-∆modulatorsinglebitquantizer. . . . . . . . . . . . . . . 52
4.9 Σ-∆modulatorsinglebitquantizerwaveformrepresentation. 52
4.10 GeneralarchitectureoftheproposedVMA[33]. . . . . . . . . 53
4.11 Qualitativelarge-signalClass-ABoperation[33]. . . . . . . . 54
4.12 Type1Class-ABcurrentamplifier[33]. . . . . . . . . . . . . . 55
4.13 Type2Class-ABcurrentamplifier[33]. . . . . . . . . . . . . . 55
4.14 SVMAschematicduringoffphase(A)andonphase(B). . . 57
5.1 Reduced Testbench schematic used in the optimization pro-
cesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.2 Differential output voltage waveforms during the integra-
tion phase for input differential voltage ranging from 0 to
-1V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.3 Differential output voltage (Red) and its derivative (Yellow)
representationobtainedfromFig.5.2. . . . . . . . . . . . . . . 60
5.4 HighlevelsimulationresultsfortwodesigncasesofFig.5.1. 61
5.5 SCΣ-∆modulatorfirststageschematicshowingrelevantis-
suesregardingthesamplerswitches. . . . . . . . . . . . . . . 62
5.6 SC Σ-∆ modulator second and third stage schematic illus-
tratingtheswitchedOpAmpactionontheswitchingscheme. 63
5.7 Qualitative transient response of the VMA differential out-
putvoltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.8 Type 1 differential output voltage waveform with K = 4
AB
andI = 150µA. . . . . . . . . . . . . . . . . . . . . . . . . . 67
tail
5.9 Type 1 differential output voltage waveform with K = 8
AB
andI = 150µA. . . . . . . . . . . . . . . . . . . . . . . . . . 67
tail
5.10 Type1differentialoutputvoltagewaveformsforafixedVin
DIFF
stepof1VandI equalto150,100and50µA. . . . . . . . 68
tail
5.11 Type 2 differential output voltage waveform with K = 4
AB
andI = 150µA. . . . . . . . . . . . . . . . . . . . . . . . . . 69
tail
viii
5.12 Type2differentialoutputvoltagewaveformsforafixedVin
DIFF
stepof1VwithI of150µAandK equalto3,4and6.. 69
tail AB
5.13 Type 2 differential output voltage waveform with K = 4
AB
andI = 100µA. . . . . . . . . . . . . . . . . . . . . . . . . . 70
tail
5.14 SCΣ-∆Melectricalsimulations(Cadence),whichrepresents
7 days of computing for 16 cycles with the ideal versions of
the quantizer and the switching network, versus the maxi-
mum of 20 minutes spent in the bottom-up approach (sim-
plifiedCadencetestbenchandPythoncodesimulation). . . . 73
ix
List of Tables
1.1 Initial specifications and characteristics of the Σ-∆ Modula-
torofthisthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 Σ-∆ModulatorSNDRsimulatedunderprocessandtemper-
aturevariations. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2 Σ-∆ModulatorSNDRmeasurementsacrosstemperature. . 24
3.1 Σ-∆ Modulator simulation time comparison on 12 GHz/24
CPUsx86_64machine. . . . . . . . . . . . . . . . . . . . . . . 26
3.2 SNDRpeakvalueforvariousΣ-∆Modulatorconfigurations,
consideredinthiswork. . . . . . . . . . . . . . . . . . . . . . 33
3.3 ExtractedoutputsamplesoftheGridsearchalgorithm. . . . 35
3.4 Selected set of coefficients for the 3rd order Σ-∆ Modulator
ofthiswork. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.5 Gaincoefficientsgeneratedforthemismatchsensitivitytest. 38
3.6 CapacitorsizingfortheSCΣ-∆M. . . . . . . . . . . . . . . . 43
5.1 CapacitorvaluesusedinFig.5.1. . . . . . . . . . . . . . . . . 59
5.2 SVMAcandidatesperformanceforK = 6andI = 200µA. 65
AB tail
5.3 Type1exploreddesignspace. . . . . . . . . . . . . . . . . . . 68
5.4 Type2exploreddesignspace. . . . . . . . . . . . . . . . . . . 70
5.5 2nd and3rd SVMAstagesscaledown. . . . . . . . . . . . . . 71
5.6 Simulated dynamic current consumption of each SC Σ-∆M
implementedforbothSVMAtypes. . . . . . . . . . . . . . . 71
5.7 SCΣ-∆MType2simulationacrosscorners. . . . . . . . . . . 72