design issues in high performance floating point arithmetic units

162 Pages·1998·0.69 MB·English

DESIGN ISSUES IN HIGH
PERFORMANCE FLOATING
POINT ARITHMETIC UNITS
Stuart Franklin Oberman
Technical Report: CSL-TR-96-711
December 1996
This work was supported by NSF under contract MIP93-13701.
DESIGN ISSUES IN HIGH PERFORMANCE FLOATING POINT
ARITHMETIC UNITS
by
Stuart Franklin Oberman
Technical Report: CSL-TR-96-711
December 1996
Computer Systems Laboratory
Departments of Electrical Engineering and Computer Science
Stanford University
Stanford, California 94305-9040
Abstract
In recent yearscomputer applications haveincreased in their computational complexity.
The industry-wide usage of performance benchmarks, such as SPECmarks,forces processor
designers to pay particular attention to implementation of the (cid:13)oating point unit, or FPU.
Special purpose applications, such as high performance graphics rendering systems, have
placed further demands on processors. High speed (cid:13)oating point hardware is a requirement
to meet these increasing demands. This work examines the state-of-the-art in FPU design
and proposes techniques for improving the performance and the performance/area ratio of
future FPUs.
In recent FPUs, emphasis has been placed on designing ever-faster adders and mul-
tipliers, with division receiving less attention. The design space of FP dividers is large,
comprising (cid:12)ve di(cid:11)erent classes of division algorithms: digit recurrence, functional itera-
tion, very high radix, table look-up, and variable latency. While division is an infrequent
operation even in (cid:13)oating point intensive applications, it is shown that ignoring its imple-
mentationcanresultin systemperformancedegradation. Ahigh performanceFPUrequires
a fast and e(cid:14)cient adder, multiplier, and divider.
The design question becomes how to best implement the FPU in order to maximize
performance given the constraints of silicon die area. The system performance and area
impact of functional unit latency is examined for varying instruction issue rates in the
context of the SPECfp92 application suite. Performance implications are investigated for
shared multiplication hardware, shared square root, on-the-(cid:13)y rounding and conversion
and fused functional units. Due to the importance of low latency FP addition, a variable
latency FPaddition algorithm has been developed which improves averageaddition latency
by 33% while maintaining single-cycle throughput. To improve the performance and area
of linear converging division algorithms, an automated process is proposed for minimizing
the complexity of SRT tables. To reduce the average latency of quadratically-converging
division algorithms,the technique ofreciprocal caching is proposed, alongwith a method to
reduce the latency penalty for exact rounding. A combination of the proposed techniques
provides a basis for future high performance (cid:13)oating point units.
Key Words and Phrases: Addition, computer arithmetic, division, (cid:13)oating point,
rounding, variable latency
(cid:13)c Copyright 1997 by Stuart Franklin Oberman
All Rights Reserved
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Acknowledgments
This work would not have been possible without the help of many wonderful people.
I would liketo thank my advisor, Michael Flynn, for all of his technical, (cid:12)nancial,
and personal support during my years at Stanford. He believed in my abilities from
my (cid:12)rst day at Stanford, and he has been a source of encouragement ever since.
I would like to thank my other readers Mark Horowitz and Cal Quate for their
e(cid:11)orts to review the drafts of this dissertation. Mark Horowitz provided constructive
advice and acted as a reality-checkfor manyof my ideas, improvingboth the content
and clarityof this research. Thanks to Martin Morf for the many discussions yielding
interesting ideas.
Thanks to Nhon Quach and Grant McFarland. I learned many of the \tricks"
of fast (cid:13)oating point from Nhon Quach, and these have in(cid:13)uenced the direction of
this research. Grant McFarland was always there to discuss a new idea or to read a
draft of a paper. Thanks to the other members of Professor Flynn’s group for their
comments and discussions: Kevin Nowka, Hesham Altwaijry, Dan Zucker, Kevin
Rudd, and Steve Fu. Thanks also to the skeptics in the group who kept me honest
and often understood the subjects better than I: Gary Bewick, Andrew Zimmerman,
Brian Flachs, and John Johnson.
I extend sincere gratitude to my family. To my loving wife, Joy, who sacri(cid:12)ced a
more comfortable living, helped support us, and ultimately helped drive me to the
completion of this work. To my mother, father, and sister who have always been
a tremendous source of encouragement, con(cid:12)dence, and love. This dissertation is
dedicated to them.
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Contents
Acknowledgments iii
1 Introduction 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Design Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 A System Perspective 6
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 System Level Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.1 Instrumentation . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.2 Method of Analysis . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.1 Instruction Mix . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.2 Compiler E(cid:11)ects . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.3 Performance and Area Tradeo(cid:11)s . . . . . . . . . . . . . . . . . 11
2.3.4 Shared Multiplier E(cid:11)ects . . . . . . . . . . . . . . . . . . . . . 17
2.3.5 Shared Square Root . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.6 On-the-(cid:13)y Rounding and Conversion . . . . . . . . . . . . . . 19
2.3.7 Consumers of Division Results . . . . . . . . . . . . . . . . . . 21
2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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3 Faster FP Addition 25
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2 FP Addition Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.1 Basic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.2 Two-Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2.3 Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2.4 Combined Rounding . . . . . . . . . . . . . . . . . . . . . . . 30
3.3 Variable Latency Algorithm . . . . . . . . . . . . . . . . . . . . . . . 32
3.3.1 Two Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.3.2 One Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.4 Performance Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4 Division Algorithms 43
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2 Digit Recurrence Algorithms . . . . . . . . . . . . . . . . . . . . . . . 44
4.2.1 De(cid:12)nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.2.2 Implementation of Basic Scheme. . . . . . . . . . . . . . . . . 46
4.2.3 Increasing Performance . . . . . . . . . . . . . . . . . . . . . . 51
4.2.4 Quotient Conversion . . . . . . . . . . . . . . . . . . . . . . . 62
4.2.5 Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.3 Functional Iteration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.3.1 Newton-Raphson . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.3.2 Series Expansion . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.4 Very High Radix Algorithms . . . . . . . . . . . . . . . . . . . . . . . 69
4.4.1 Accurate Quotient Approximations . . . . . . . . . . . . . . . 69
4.4.2 Short Reciprocal . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.4.3 Rounding and Prescaling . . . . . . . . . . . . . . . . . . . . . 74
4.5 Look-up Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.5.1 Direct Approximations . . . . . . . . . . . . . . . . . . . . . . 76
4.5.2 Linear Approximations . . . . . . . . . . . . . . . . . . . . . . 78
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4.5.3 Partial Product Arrays . . . . . . . . . . . . . . . . . . . . . . 79
4.6 Variable Latency Algorithms . . . . . . . . . . . . . . . . . . . . . . . 80
4.6.1 Self-Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.6.2 Result Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.6.3 Speculation of Quotient Digits . . . . . . . . . . . . . . . . . . 83
4.7 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5 Faster SRT Dividers 91
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.2 SRT Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.3 Implementing SRT Tables . . . . . . . . . . . . . . . . . . . . . . . . 92
5.3.1 Divisor and Partial Remainder Estimates . . . . . . . . . . . . 92
5.3.2 Uncertainty Regions . . . . . . . . . . . . . . . . . . . . . . . 95
5.3.3 Reducing Table Complexity . . . . . . . . . . . . . . . . . . . 97
5.4 Experimental Methodology . . . . . . . . . . . . . . . . . . . . . . . . 98
5.4.1 TableGen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.4.2 Table Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.5 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.5.1 Same Radix Tradeo(cid:11)s . . . . . . . . . . . . . . . . . . . . . . 102
5.5.2 Higher Radix . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6 Division and Reciprocal Caches 110
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.2 Reciprocal Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.2.1 Iterative Division . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.2.2 Experimental Methodology . . . . . . . . . . . . . . . . . . . . 112
6.2.3 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3 Division Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.4 Square Root Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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7 Fast Rounding 120
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
7.2 IEEE Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7.3 Division by Functional Iteration . . . . . . . . . . . . . . . . . . . . . 122
7.4 Previously Implemented Techniques . . . . . . . . . . . . . . . . . . . 124
7.5 Reducing the Frequency of Remainder Computations . . . . . . . . . 126
7.5.1 Basic Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7.5.2 Faster Rounding . . . . . . . . . . . . . . . . . . . . . . . . . 130
7.5.3 Higher Performance . . . . . . . . . . . . . . . . . . . . . . . . 131
7.6 Faster Magnitude Comparison . . . . . . . . . . . . . . . . . . . . . . 133
7.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
8 Conclusion 136
8.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
8.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Bibliography 141
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