Design and implementation of a low-noise high-linearity variable gain amplifier for high speed ...

99 Pages·2012·2.27 MB·English

Institutionen för systemteknik

Department of Electrical Engineering

Examensarbete

Design and implementation of a low-noise high-linearity
variable gain amplifier for high speed transceivers

Master Thesis in Division of Electronics Systems
at Linköping Institute of Technology
by

Rehan Azmat

LiTH-ISY-EX--11/4543--SE
21st December, 2011

TEKNISKA HÖGSKOLAN
LINKÖPINGS UNIVERSITET
Department of Electrical Engineering Linköpings tekniska högskola
Linköping University Institutionen för systemteknik
S-581 83 Linköping, Sweden 581 83 Linköping
Master thesis performed in
Fraunhofer Institute for Integrated Circuits (IIS)
Erlangen, Germany

Design and implementation of a low-noise high-linearity
variable gain amplifier for high speed transceivers

Master Thesis in Division of Electronics Systems
at Linköping Institute of Technology
by

Rehan Azmat

LiTH-ISY-EX--11/4543--SE

Supervisor: Supervisor:

Conrad Zerna Dr J. Jacob Wikner
Optical Sensors and Communications Department of Electrical Engineering
Fraunhofer Institute for Integrated Circuits (IIS) Linköping University
Erlangen, Germany Linköping, Sweden
[email protected] jacob.wikner @ liu.se

Examiner:

Dr. Mark Vesterbacka
Department of Electrical Engineering (ISY)
Linköping University
Linköping, Sweden
mark.vesterbacka @ liu.se

Date: 21st December, 2011.
Presentation Date Department and Division
Department of Electrical Engineering
2011 – 12 - 21 Division of Electronics Systems
Publishing Date (Electronic version) Linköping University
SE-581 83, Linkoping, Sweden
2012 – 02 - 02

Language Type of Publication
ISBN (Licentiate thesis)

English Licentiate thesis
ISRN: LiTH-ISY-EX--11/4543--SE
Other (specify below) Degree thesis

Thesis C-level Title of series (Licentiate thesis)
Thesis D-level
Report
Number of Pages Other (specify below) Series number/ISSN (Licentiate thesis)
95

URL, Electronic Version
http://www.ep.liu.se
http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-73449

Publication Title

Design and implementation of a low-noise high-linearity variable gain amplifier for high speed
transceivers.

Author(s)
Rehan Azmat

Abstract

The variable gain amplifier (VGA) is utilized in various applications of remote sensing and
communication equipments. Applications of the variable gain amplifier (VGA) include radar,
ultrasound, wireless communication and even speech analysis. These applications use the variable gain
amplifier (VGA) to enhance dynamic performance.
The purpose of the thesis work is to implement a high linearity and low noise variable gain amplifier in
150 nm CMOS technology, for an analog-front-end of a transceiver. Two different amplifier
architectures are designed and compared. First architecture is an amplifier with diode connected load
and second architecture is a source degenerative amplifier. The performance of the amplifier with diode
connected load is lower than the source degenerative amplifier in terms of gain, power, linearity, noise
and bandwidth. So, the source degenerative amplifier is selected for implementation. The three stage
variable gain differential amplifier is implemented with selected architecture.
The implemented three stage variable gain differential amplifier have gain range of -541.5 mdB to
22.46 dB with step size of approximately 0.3 dB and total gain steps are 78. The -3 dB bandwidth
achieved is 953.3 MHz. The third harmonic distortion (HD3) is -45 dBc at 250 mV and the power is 35
mW at 1.8 V supply source.

Keywords
Transceiver, Analog, Amplifier, Linearity, Noise, Gain, Bandwidth, VGA, CMOS, HD3.
Linköping University Electronic Press

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© Rehan Azmat.
Abstract
The variable gain amplifier (VGA) is utilized in various applications of remote sensing and
communicationequipments. Applicationsofthevariablegainamplifier(VGA)includeradar,
ultrasound, wireless communication and even speech analysis. These applications use the
variable gain amplifier (VGA) to enhance dynamic performance.
The purpose of the thesis work is to implement a high linearity and low noise variable gain
amplifier in 150 nm CMOS technology, for an analog-front-end of a transceiver. Two dif-
ferent amplifier architectures are designed and compared. First architecture is an amplifier
with diode connected load and second architecture is a source degenerative amplifier. The
performanceoftheamplifierwithdiodeconnectedloadislowerthanthesourcedegenerative
amplifierintermsofgain,power,linearity,noiseandbandwidth. So,thesourcedegenerative
amplifier is selected for implementation. The three stage variable gain differential amplifier
is implemented with selected architecture.
Theimplementedthreestagevariablegaindifferentialamplifierhavegainrangeof−541.5mdB
to 22.46 dB with step size of approximately 0.3 dB and total gain steps are 78. The −3 dB
bandwidth achieved is 953.3 MHz. The third harmonic distortion (HD3) is −45 dBc at
250 mV and the power is 35 mW at 1.8 V supply source.
1
Acknowledgement
IowemydeepestgratitudetoalmightyAllah, whoblessedmewithstrength, determination
and devotion to accomplish this thesis.
It is an honour for me to work in Fraunhofer Institute for Integrated Circuits (IIS). I am
heartilythankfultomysupervisor,ConradZernaforgivingmethisopportunity. Hereceived
me at my arrival in Germany and arranged a nice accommodation for me. He also guided
metosolvetheproblemsemergedduringthethesis. Thistaskwouldnothavebeenpossible
without his support, encouragement and guidance.
IwouldliketothankmysupervisorDrJ.JacobWikner,whosehelp,adviceandsupervision
was invaluable throughout the thesis work.
IalsowishtothankmyfriendandcolleagueChoudharyJabbarYounisforhisencouragement
to do a thesis outside Sweden. He also helped me during thesis application process. We
workedonsamechipbutdifferentblocks. Wehadmanycooperativediscussionsthroughout
our thesis work.
Finally, words alone cannot express the gratitude I owe to my family, especially my loving
parents for their support and prayers.
2
Contents
List of Abbreviations 3
List of Figures 5
List of Tables 7
1 Introduction 8
1.1 Overview of system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Analog Front End 11
2.1 Variable gain amplifier (VGA) . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.1 Design Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.1.1 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.1.2 Non Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.1.3 Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1.1.4 Transistor type . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1.2 Simulation Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.2.1 Normal Operation Simulation . . . . . . . . . . . . . . . . . 19
2.2 Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 Variable Gain Amplifier Architectures 22
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Selected Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 Differential amplifier with diode connected load . . . . . . . . . . . . . . . . . 23
3.4 Differential amplifier with source degeneration. . . . . . . . . . . . . . . . . . 28
3.5 Comparisonofdifferentialamplifierwithdiodeconnectedloadanddifferential
amplifier with source degeneration . . . . . . . . . . . . . . . . . . . . . . . . 33
3.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4 Three stage differential VGA with resistive network and source degener-
ation 35
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2 Coarse stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3 Fine stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.3.1 Fine stage version 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.3.1.1 Constant (g ) biasing circuit . . . . . . . . . . . . . . . . . . 42
m
4.3.1.2 Simulation results of the fine stage version 1 . . . . . . . . . 47
1
2
4.3.2 Fine stage version 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3.3 Fine stage version 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.4 Output buffer design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.5 Gain setting decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.6 Offset compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.6.1 First stage offset compensation amplifier . . . . . . . . . . . . . . . . . 62
4.6.2 Second stage offset compensation amplifier . . . . . . . . . . . . . . . 65
4.7 Three stage differential VGA with output buffer, gain setting decoder and
offset compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5 Layout design of the three stage variable gain differential amplifier with
output buffer 71
5.1 Coarse stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
5.2 Fine stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.3 Output buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.4 Threestagevariablegaindifferentialamplifierwithoutputbuffer,gainsetting
decoder and offset compensation . . . . . . . . . . . . . . . . . . . . . . . . . 79
6 Future work 84
6.1 VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.2 Fine stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.3 Coarse stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.4 Offset compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.5 Constant transconductance biasing circuit . . . . . . . . . . . . . . . . . . . . 85
6.6 Three stage variable gain differential amplifier with output buffer . . . . . . . 85
A Simulation Plan 86
A.1 Normal Operation Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
B Gain setting decoder verilogA code 89
The bibliography 93
3
List of Abbreviations
VGA: Variable gain amplifier.
AFE: Analog front end.
ADC: Analog to digital converter.
SNR: Signal to noise ratio.
DSP: Digital signal processor.
PAM: Pulse amplitude modulation.
EMI: Electromagnetic interference.
AVGA: Analog variable gain amplifier.
DVGA: Digital variable gain amplifier.
MOSFET: Metal oxide semiconductor field effect transistor.
DFT: Discrete Fourier transform.
AC: Alternating current.
DC: Direct current.
HD3: Third harmonic distortion.
CMFB: Common mode feedback.
dB: Decibel.
dBc: Carrier normalize decibel.
PMOS: P type metal oxide semiconductor transistor.
NMOS: N type metal oxide semiconductor transistor.
Vgs: Gate to source voltage.
R: Resistance.
gm: Transconductance.
RC: Resistance and capacitance.
List of Figures
1.1 Block diagram of the transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 Pulse amplitude modulated signal. . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 Testing of the common mode rejection using cable clamp. . . . . . . . . . . . 10
2.1 Analog front end (AFE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Gain control curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Thermal Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Long channel MOSFET, thermal noise model. . . . . . . . . . . . . . . . . . . 14
2.5 Reduction of the gate resistance to minimize the noise. . . . . . . . . . . . . . 15
2.6 Flicker noise spectrum. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.7 Non linearity phenomenon. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.8 Common source amplifier with source regeneration. . . . . . . . . . . . . . . . 17
2.9 Analog-to-digital converter (ADC) block diagram. . . . . . . . . . . . . . . . 21
3.1 Transistor level schematic of the differential amplifier with diode connected
load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 Small signal model of the differential amplifier with diode connected load. . . 23
3.3 Half circuit, small signal model of the differential amplifier with diode con-
nected load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4 Transistor level schematic of the differential amplifier with diode connected
load and CMFB circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5 GaincurvesofthedifferentialamplifierwithdiodeconnectedloadandCMFB
circuit in the corner analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.6 Schematic of the differential amplifier with source degeneration. . . . . . . . . 28
3.7 Small signal model of the differential amplifier with source degeneration. . . . 29
3.8 Half circuit, small signal model of the differential amplifier with source de-
generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.9 Gaincurvesofthedifferentialamplifierwithsourcedegenerationinthecorner
analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1 Block diagram of the three stage differential amplifier with output buffer. . . 35
4.2 Schematic of the coarse stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3 Gain curves of the coarse stage in the corner analysis. . . . . . . . . . . . . . 38
4.4 Schematic of the fine stage with constant gm biasing.. . . . . . . . . . . . . . 41
4.5 Schematic of the constant transconductance biasing circuit. . . . . . . . . . . 42
4.6 Schematicoftheamplifierusedintheconstanttransconductancebiasingcircuit. 43
4.7 Schematic of the complete constant transconductance biasing circuit. . . . . . 44
4.8 Gain curves of the fine stage with constant gm biasing in the corner analysis. 47
4.9 Gain setting curves of the fine stage with constant gm biasing in the corner
analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4