Design and debugging of multi-step analog to digital converters

192 Pages·2017·3.27 MB·English

Design and debugging of multi-step analog to digital
converters
Citation for published version (APA):
Zjajo, A. (2010). Design and debugging of multi-step analog to digital converters. [Phd Thesis 1 (Research TU/e
/ Graduation TU/e), Electrical Engineering]. Technische Universiteit Eindhoven. https://doi.org/10.6100/IR657787
DOI:
10.6100/IR657787
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Published: 01/01/2010
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Download date: 12. Jan. 2023
DESIGN AND DEBUGGING OF MULTI-STEP
ANALOG TO DIGITAL CONVERTERS

Amir Zjajo
The work described in this thesis has been carried out at the Philips Research Laboratories
and Corporate Research of NXP Semiconductors, both in Eindhoven, The Netherlands, as
part of the Philips Research and NXP Semiconductors Research Program

Front cover: A/D converter described in this thesis

Printed by Universiteitsdrukerij Technische Universiteit Eindhoven
ISBN: 978-90-386-2156-2

Copyright © 2010 by Amir Zjajo

All rights reserved. No part of the material protected by this copyright notice may be repro-
duced or utilized in any form or by any means, electronic or mechanical, including photo-
copying, recording or by any information storage and retrieval system, without the prior
permission of the author.
DESIGN AND DEBUGGING OF
MULTI-STEP ANALOG TO DIGITAL CONVERTERS

PROEFSCHRIFT

ter verkrijging van
de graad van doctor aan de Technische Universiteit Eindhoven,
op gezag van de rector magnificus, prof.dr.ir. C.J. van Duijn,
voor een commissie aangewezen door het College voor Promoties
in het openbaar te verdedigen op maandag 22 februari 2010 om 16.00 uur

door

Amir Zjajo

geboren te Jajce, Bosnië-Herzegovina
Dit proefschrift is goedgekeurd door de promotor:

prof.dr. J. Pineda de Gyvez
To my father
Dit proefschrift is goedgekeurd door de promotor:

Prof.dr. J. Pineda de Gyvez

Samenstelling promotiecommissie:

Prof.dr.ir. A.C.P.M. Backx Voorzitter
Prof.dr.ir. R.H.J.M. Otten Technische Universiteit Eindhoven
Prof.dr. A. Rueda University of Sevilla
Prof.dr.ir. A.H.M. van Roermund Technische Universiteit Eindhoven
Dr.ir. H.G. Kerkhoff Universiteit Twente
Prof.dr. J.R. Long Technische Universiteit Delft
CONTENTS

List of Abbrevations.................................................................................................................................................ix
List of Symbols..........................................................................................................................................................xi
Introduction..................................................................................................................................1-1
1.1. A/D Conversion Systems................................................................................................................1-1
1.2. Remarks on Curent Design and Debugging Practice..................................................................1-4
1.3. Motivation...........................................................................................................................................1-7
1.4. Organization of the Thesis..............................................................................................................1-8
Multi-Step A/D Converter Design..................................................................................................2-9
2.1. High-Speed High-Resolution A/D Converter Architectural Choices.....................................2-9
2.2. Multi-Step A/D Converter Architecture.....................................................................................2-16
2.3. Error Sources in Multi-Step A/D Converter.............................................................................2-16
2.4. Time-Interleaved Front-End Sample-and-Hold Circuit...........................................................2-18
2.4.1. Time-Interleaved Architecture.......................................................................................2-18
2.4.2. Matching of Sample-and-Hold Units...........................................................................2-21
2.4.3. Circuit Design...................................................................................................................2-25
2.5. Multi-Step A/D Converter Stage Design....................................................................................2-30
2.5.1. Coarse Quantization........................................................................................................2-30
2.5.2. Fine Quantization............................................................................................................2-34
2.6. Inter-Stage Design and Calibration..............................................................................................2-40
2.6.1. Sub-D/A Converter Design...........................................................................................2-40
2.6.2. Residue Amplifier............................................................................................................2-42
2.7. Experimental Results......................................................................................................................2-48
2.8. A/D Converters Realization Comparison..................................................................................2-52
2.9. Conclusion........................................................................................................................................2-52
Design and Debugging of Multi-Step Analog to Digital Converters vii
Multi-Step A/D Converter Testing...............................................................................................3-57
3.1. Analog Automatic Test Pattern Generation for Quasi-Static Structural Test......................3-57
3.1.1. Test Strategy Definition..................................................................................................3-59
3.1.2. Linear Fault Model based on Quasi-Static Nodal Voltage Approach....................3-60
3.1.3. Decision Criteria and Test-Stimuli Optimization.......................................................3-69
3.2. Design for Testability Concept.....................................................................................................3-73
3.2.1. Power-Scan Chain DfT...................................................................................................3-75
3.2.2. Application Example.......................................................................................................3-80
3.3. BIST using a Highly Linear On-Chip Waveform Generator...................................................3-87
3.5. Conclusion........................................................................................................................................3-87
Debugging of Multi-Step A/D Converters....................................................................................4-95
4.1. Concept of Sensor Networks........................................................................................................4-95
4.1.1. Observation Strategy.......................................................................................................4-96
4.1.2. Integrated Sensor.............................................................................................................4-98
4.1.3. Decision Window and Application Limits...............................................................4-101
4.1.4. Die-Level Process Monitor Circuit Design..............................................................4-104
4.1.5. Temperature Sensor.....................................................................................................4-109
4.2. Estimation of Die-Level Process Variations............................................................................4-112
4.2.1. Expectation-Maximization Algorithm.......................................................................4-112
4.2.2. Support Vector Machine Limits Estimator..............................................................4-114
4.3. Debugging of Multi-Step A/D Converter Stages...................................................................4-116
4.4.. Debugging of Time-Interleaved Systems................................................................................4-126
4.5. Foreground Calibration ..............................................................................................................4-126
4.6. Experimental Results...................................................................................................................4-130
4.7. Conclusion.....................................................................................................................................4-140
Conclusions and Recommendations.............................................................................................5-141
5.1. Summary of Results.....................................................................................................................5-141
5.2. Original Contribution of This Thesis........................................................................................5-142
5.3. Recommendations and Future Research..................................................................................5-143
Appendix.................................................................................................................................................................145
References...............................................................................................................................................................155
List of Publications................................................................................................................................................169
Summary..................................................................................................................................................................171
Samenvatting...........................................................................................................................................................173
Acknowledgments..................................................................................................................................................175
About the Author...................................................................................................................................................177
Design and Debugging of Multi-Step Analog to Digital Converters viii
LIST OF ABBREVATIONS

A/D Analog to Digital
ADC Analog to Digital Converter
ADSL Asynchronous DSL
ATE Automatic Test Equipment
ATPG Automatic Test Pattern Generator
BIST Built-In Self-Test
CAD Computer Aided Design
CDMA Code Division Multiple Access
CMFB Common-Mode Feedback
CMOS Complementary MOS
CMRR Common-Mode Rejection Ratio
CPU Central Processing Unit
D/A Digital to Analog
DAC Digital to Analog Converter
DAE Differential Algebraic Equations
DEM Dynamic Element Matching
DFT Discrete Fourier Transform
DfT Design for Testability
DIBL Drain-Induced Barrier Lowering
DLPM Die-Level Process Monitor
DMT Discrete Multi Tone
DNL Differential Non-Linearity
DR Dynamic Range
DSL Digital Subscriber Line
DSP Digital Signal Processor
DTFT Discrete Time Fourier Transform
DUT Device under Test
EM Expectation-Maximization
ENOB Effective Number of Bits
ERBW Effective Resolution Bandwidth
ESSCIRC European Solid-State Circuit Conference
FFT Fast Fourier Transform
FoM Figure of Merit
FPGA Field Programmable Gate Array
GBW Gain-Bandwidth Product
GSM Global System for Mobile Communication
Design and Debugging of Multi-Step Analog to Digital Converters ix