Demonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI

13 Pages·2010·2.5 MB·English

308 IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.46,NO.1,JANUARY2011
Demonstration of Integrated Micro-Electro-
Mechanical Relay Circuits for VLSI Applications
Matthew Spencer, Fred Chen, ChengC.Wang,StudentMember,IEEE, RhesaNathanael,StudentMember,IEEE,
HosseinFariborzi,StudentMember,IEEE, AbhinavGupta, Hei Kam,Member,IEEE, VincentPott,Member,IEEE,
JaeseokJeon, Tsu-Jae King Liu, Fellow, IEEE, DejanMarkovic´, Member, IEEE, Elad Alon, Member, IEEE,
and VladimirStojanovic´, Member, IEEE
Abstract—Thisworkpresentsmeasuredresultsfromtestchips Unfortunately, even this parallelism will eventually be-
containing circuits implemented with micro-electro-mechanical come ineffective as each CMOS functional unit approaches
(MEM) relays. The relay circuits designed on these test chips its throughput-independent, minimum achievable energy. The
illustratearangeofimportantfunctionsnecessaryfortheimple-
minimum energy in CMOS is limited by the sub-threshold
mentationofintegratedVLSIsystemsandlendinsightintocircuit
leakage of the transistors because once CMOS circuits enter
design techniques optimized for the physical properties of these
devices. To explore these techniques a hybrid electro-mechanical the sub-threshold regime, an increase in the threshold voltage
modeloftherelays’electricalandmechanicalcharacteristicshas decreasestheleakagecurrentbyexactlythesameamountthat
beendeveloped,correlatedtomeasurements,andthenalsoapplied it increases the delay. The only mechanism left to tune both
topredictMEMrelayperformanceifthetechnologywerescaled
the leakage and dynamic energy components is therefore the
to a 90 nm technology node. A theoretical, scaled, 32-bit MEM
supplyvoltage,whichcannotbereducedbelowacertainvalue
relay-based adder, with a single-bit functionality demonstrated
bythemeasuredcircuits,isfoundtoofferafactoroftenenergy (setby andthecircuit’sactivityfactorandlogicdepth)
efficiencygainoveranoptimizedCMOSadderforsub-20MOPS withoutincreasingthetotalenergy[1].
throughputsatamoderateincreaseinarea. If a device with significantly improved leakage charac-
IndexTerms—Adders,digitalcircuits,MEMrelays,microelec- teristics (i.e., steeper sub-threshold slope) were available,
tromechanical devices, minimum energy point, very-large-scale major improvements in energy efficiency over CMOS could
integration. be achieved [2]. Many researchers have therefore been ex-
ploringnewswitchingdeviceconceptstoachievesub-threshold
slopes steeper than the limit set by in field-effect or
I. INTRODUCTION
bipolar-junction transistors [3], [4]. However, many of these
A LTHOUGH CMOS technology scaling has historically devices achieve sharp sub-threshold slope over only a limited
enabled significantly reduced energy-per-operation in range of supply voltage, leading to relatively poor on-to-off
integrated circuits, today’s designs are increasingly power current ratios and/or very low on-state current at low supply
limited in ways that technology scaling cannot alleviate. This voltages.
hasoccurredbecausethethresholdvoltageofthetransistorshas Inthiscontext,micro-electro-mechanical(MEM)relaysap-
alreadybeenscaledtothevaluethatoptimallybalancesleakage pearveryattractive,havingrecentlydemonstratedon-to-offcur-
energy and dynamic energy, and hence further reductions in rentratiosoftenordersofmagnitudeoverinputswingsofone
the threshold voltage would actually increase the amount of millivoltandimmeasurablylowleakagecurrents[5].Thesere-
energy consumed per operation. With the threshold voltage lays are four-terminal devices that are functionally similar to
pinnedbecauseofsub-thresholdleakage,furthersupplyvoltage CMOStransistors.DespitetheirnearlyidealI-Vcharacteristics,
scalingcomesattheexpenseofper-coreperformance,forcing thetimerequiredtomechanicallyswitcharelayfromtheoff-to
atrendtowardsincreasinglyparallelcircuitimplementationsas theon-stateissignificantlylongerthantheelectricalswitching
theonlymeanstoefficientlyimprovethroughput. delayofanequivalentCMOSdevice.Specifically,relaysfabri-
catedina90nmtechnologynodearepredictedtohavedelays
of 10’s of nanoseconds compared to 100’s of picoseconds for
ManuscriptreceivedApril20,2010;revisedJuly05,2010;acceptedJuly16,
transistorsinathresholdoptimizedCMOSprocessoperatingin
2010.DateofpublicationNovember01,2010;dateofcurrentversionDecember
27,2010.ThispaperwasapprovedbyGuestEditorAlisonBurdett.Thiswork thesub-thresholdregime,oruptonanosecondsinamoregener-
wassupportedinpartbytheDARPANEMSprogram,theC2S2andMSDFCRP icallyavailableCMOSprocess.Althoughthelargemechanical
centers,MITCICS,UCLAICSL,BWRC,andNSFInfrastructureGrantNo.
delayof MEM relayssuggests thatMEM relay circuits would
040327.
M.Spencer,R.Nathanael,A.Gupta,H.Kam,V.Pott,J.Jeon,T.-J.King haveverypoorperformance,wehaveproposedcircuitarchitec-
Liu,andE.AlonarewiththeUniversityofCalifornia,Berkeley,CA94720 tures that significantly mitigate this by implementing logic as
USA(e-mail:[email protected]).
large, complex gates that minimize the number of mechanical
F.Chen,H.Fariborzi,andV.Stojanovic´arewiththeMassachusettsInstitute
ofTechnology,Cambridge,MA02142USA. delaysonthecriticalpath[6].
C. C. Wang and D. Markovic´ are with the University of California, To verify these circuit principles and the feasibility of the
LosAngeles,CA90095USA. MEMrelaytechnology,thispaperdescribesatestchipdemon-
Colorversionsofoneormoreofthefiguresinthispaperareavailableonline
strating several functioning MEM-relay circuits [7]. Results
athttp://ieeexplore.ieee.org.
DigitalObjectIdentifier10.1109/JSSC.2010.2074370 fromthetestchipconfirmMEM-relaydelaycharacteristicsand
0018-9200/$26.00©2010IEEE
SPENCERetal.:DEMONSTRATIONOFINTEGRATEDMICRO-ELECTRO-MECHANICALRELAYCIRCUITS 309
demonstratefunctionalityofkeycircuitcomponentsneededfor
the development of an integrated VLSI system: logic, latches,
memory,andI/Ocircuits.
Toquantifytheimpactofdevicetopologyanddimensionson
MEMcircuits,scalablemodelsoftheMEMrelaybehaviorare
developedandusedtodriveacomparisonbetweenthepredicted
capabilities of scaled MEM relays and CMOS in an equiva-
lent90nmtechnologynode.Acomparisonofoptimized32-bit
adders built from CMOS and MEM relays indicates that de-
spitetheirlargemechanicaldelay,MEMrelayscanachieveen-
ergy-delaycharacteristicsthatarenearlyanorderofmagnitude
betterthanCMOS overa widerangeoffrequencies, whilere-
quiring only three times as much area. This further validates
thenotionthatMEMrelaysareviablecandidatesforfutureen-
ergy-efficientdigitalintegratedcircuits. Fig.1. SEM,diagram,andoperatingstatesoftheMEMrelaydevice.
The remainder of the paper is organized as follows. In
Section II we first describe the structure, operation, and mod-
eling of the MEM relays on the test chip. In Section III we conductionpath.Topreventthestructurefromcollapsingcata-
report measured results of circuits constructed from MEM strophically, the dimples in the channel restrict the gate’s mo-
relays illustrating a variety of functions. Then, in Section IV tion once they make contact with the drain and source. When
westudyhowthisMEMrelay’sperformancewouldscalewith thegate-to-bodyvoltageisreducedsufficiently,thespringsre-
devicedimensionsdowntoa90nmprocessnode,includinga turntotheirunflexedposition,pullingthechanneloutofcontact
few possible layout optimizations. Section V uses the conclu- withthedrainandsource.TheseMEMrelaydynamicscanbe
sionsaboutscaleddevicestocompareMEMrelayandCMOS accurately captured witha classical hybrid electro-mechanical
circuit performance and show that adders similar to those that model,describednext,whichsignificantlyaidsdesignintuition
havealreadybeenimplementedappearpromisingforuseinthe andenablesfastcircuitsimulationandverification.
construction of low-power VLSI blocks. Finally, Section VI
concludesthepaper. B. MechanicalModelingoftheMEMRelay
A non-linear second-order differential equation is used to
modelthemovementofthegateundertheappliedelectrostatic
II. STRUCTURE, OPERATION AND MODELING OF A
force[6],[8].Inthismodel,whichissummarizedinFig.2,the
MEMRELAY
massandflexuresaremodeledasaspring-mass-dampersystem
Inthissectionwedescribethestructureandoperationofthe whichcontrolsthevariableresistancesbetweenchannel,drain,
MEM relayinorder toprovidebackground forthe circuitand and source
scaling explorations that are the focus of this paper. We also
developahybridelectro-mechanicalmodeloftheMEMrelay, (1)
whichwewilluseforMEMrelaycircuitdesignandanalysis.
where isthedisplacementofthegate, isthedampingcoef-
ficientassociatedwiththemotionofthegatestructure, isthe
A. MEMRelayStructureandOperation
effectivespringconstantofthegatestructure,and isthe
Fig.1showsanSEMimageanddiagramoftheMEMrelay non-linearelectricalforcebetweenthegateandthebody.Both
deviceusedinthiswork[5].Thefour-terminaldeviceconsists the spring and damping coefficients in this dynamical model
ofamovablepoly-SiGegatestructuresuspendedbyspring-like must be evaluated by finite-element simulations, but if we ne-
foldedflexuresabovethetungstenbody,drain,andsourceelec- glectfringingfields,theelectricalforcecanbemodeledsimply
trodes.Thechannelconsistsofastripoftungstenattachedtoan astheelectrostaticforcebetweenthegateandbodyelectrodes
insulatingoxidelayeronthebottomofthegate.Thechanneland
gate have vertical deformations, referred to as dimples, which (2)
define the regions where contact is made between the channel
and the source and drain. To improve device reliability, a thin where isthepermittivityoffreespace, istheareaofthe
titaniumoxide(TiO )coatingisappliedtothedevicetoreduce overlapbetweenthegateandbodyelectrodes, isthenormal
currentflowatthecontactsandslowtheformationoftungsten gap between electrodes in the absence of electrical force, and
nativeoxides[8]. isthevoltagebetweenthegateandthebody.
The basic operation and switching states of the MEM relay Duringrelayactuation,thespringforce varieslinearly
arealsoshowninFig.1.Whenavoltageisappliedbetweenthe with the displacement of the gate, while the electrical force is
gate structure and the body electrode, the applied electrostatic inverselyquadraticingatedisplacement.Thisresultsinarange
force pulls against the mechanical spring force of the flexures ofdisplacementswheretheelectricalforceisalwayslargerthan
and displaces the gate vertically. When sufficient electrostatic the spring restoring force, and in this range the difference in
force is applied, the relay is turned on by the channel coming forces causes the device to unconditionally snap shut. It can
intocontactwiththesourceanddrainelectrodesandcreatinga beshownthatthecriticaldisplacementatwhichthespringand
310 IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.46,NO.1,JANUARY2011
Havingdescribedthemechanicalmodeloftherelay,itisin-
teresting to note that concerns related to environmental vibra-
tions causing spurious actuation of the relay are largely mis-
placed.Thelowmassofthestructureimpliesthatithaslowin-
ertiaandensuresthatthedevicecanonlybeactuatedbyexternal
forcesinthepresenceofverylargeaccelerations.Forinstance,
thedevicesfabricatedinthisworkwouldrequireanexternalac-
celerationof20000gtobalanceagainstthespringforce
suchthatcontactbetweenthechannelandthesource/drainelec-
trodesismade.Ifalldimensionsarescaledequally,thedevice
tendstobecomeevenmoreimmunetovibrationasitscalesbe-
cause the mass shrinks in a cubic fashion while the opposing
springforcescalesonlylinearly.
Similarly, thermal energy has little impact on device opera-
tion at the scales considered in this study. Since the structure
iseffectivelyconfinedtoone(vertical)degreeoffreedom,itis
Fig. 2. Schematic indicating the relevant components in the MEM relay
Verilog-Amodel. subjectto joules ofthermal energy.Comparing this to
the joulesofstoredspringenergy,itcanbeshownthatthe
ofdisplacementduetothermalenergyisonly pmforthe
electrical forces are equal is one third of the nominal gap dis- fabricatedrelays.Thisis0.005%ofthesizeofthecurrentactu-
tance. In the case that the total displacement defined by the ationgapandcausesnegligiblevariationinthepull-involtage.
dimples islargerthanathirdofthenominalgap ,the Thoughscalingthedeviceswillreducethespringconstantand
voltagenecessarytosnapthestructureshut—calledthepull-in the gap size, leading to a relative increase in the effect of the
voltage [9]—canbederivedtobe thermal energy displacement, the of the variation in pull-in
voltage remains less than 0.5% at the scaled dimensions con-
sideredinSectionsIVandV.
(3)
C. ElectricalModelingoftheMEMRelay
The delay required for the relay to turn on is governed by Althoughmechanicalmotiontendstodominatetheswitching
the relay dynamics described in (1). Similar to the reduced delayofasinglerelay,theoverallcircuitswitchingdelayisaf-
delayfromincreasinggateoverdriveinCMOS,alargerapplied fectedbytheelectricaldelayaswell.Predictingtheamountof
gate-to-body voltage in relays results in a larger elec- time required for a channel in the on-state to discharge a load
trical force, larger acceleration, and thus a shorter mechanical capacitancerequiresaccuratemodelingofboththeon-statere-
delay.Inaddition,themass andspringconstant ofthe sistanceandthecapacitancesofthedevice.
deviceaffecthowrapidlytheelectrostaticforcedisplacesit.As Theon-stateresistanceiscomprisedoftheresistanceofthe
developedin[10]and[11],undertypicaloperatingconditions, tungstenwiresleadingtoandfromthedevice ,there-
these effects on the mechanical turn-on delay of the sistanceofthechannel ,theresistanceofthecontactsbe-
relaycanbemathematicallymodeledby tweenthechannelandthesource/drain ,aswellasthere-
sistanceofthepassivatingoxideusedtoimprovetheendurance
ofthedevice .Ofthesecomponents,thelasttwoareby
(4)
far the most significant contributors to the total on-state resis-
tance. As summarized in [12], the resistance of the contact at
If the gate-to-body voltage is held constant as the gate is eachsideofthechanneldependsontheconditionsunderwhich
pulled in, then the amount of force applied to the gate will thecontactismadeandthepropertiesofthematerial
be higher than it was in the off-state since the effective gap is
smaller.ThiscreateshystereticbehaviorintheMEMrelay:once (5)
the device is pulled in, the absolute value of the gate-to-body
voltage must be lowered below the pull-in voltage in order to where is the resistivity of the contacting material, is the
causethedevicetoreleaseorpullout.Thishysteresiseffectis mean free path of electrons in the contact material, and is
also increased by surface forces that attract the channel to the theeffectivecontactareaasgivenby
source/drain electrodes in the contact regions. In spite of the
hysteresis,themechanicalturn-offdelayistypicallymuchfaster
than the turn-on delay because electrical contact is broken as (6)
soonasthechanneldimplemovesmorethan nmawayfrom
thesurfacewhenthedeviceisreleased.Incontrast,turningthe In(6), isthehardnessofthematerialand isthedeforma-
deviceonrequiresthatthegatemusttravelnearlytheentiregap tioncoefficient.Inthecaseofourcontacts,thematerialistung-
betweenthedimpleandthesource/drainelectrode(whichinour stenandthecontactiselastic.Theparametervaluesof
devicesis nm)beforemakingelectricalcontact. n -m, nm, , and GPa model this
SPENCERetal.:DEMONSTRATIONOFINTEGRATEDMICRO-ELECTRO-MECHANICALRELAYCIRCUITS 311
TABLEI the on-state. Both of these are well-modeled as standard par-
SCALEDANDCURRENTMEMRELAYDEVICEMODELPARAMETERS. allelplatecapacitors
MEASUREDDATAISINDICATEDWITHANASTERISK
(7)
where istherelativepermittivityofthegateoxide, is
theareaofthegatetochanneloverlap,and isthethickness
ofthegateoxide.Eventhough isrelativelysmallcompared
to ,thegate-to-channelcapacitancecanbeasignificantcon-
tributortotheoverallloadcapacitancebecauseofthehighrel-
ativepermittivityofthegateoxide—Al O inourdevices.The
channel-to-bodycapacitance, ,isnotsignificantbecauseit
isformedoverthesameairgapasthegatetobodycapacitance
buthasthesmallerareaofoverlap, .1
Alloftheothercapacitorsinthedevicemodelarisefromthe
overlapbetweenthegateandtheotherelectrodes.Theoverlap
withthedrainandsourceelectrodesintroducesgate-drain
andgate-source parasiticcapacitors.Thesearealsomod-
eledasparallel-platecapacitors,withgapsizeandpermittivity
that are the same as for the gate-to-body capacitance. Conse-
quentlytheratioof tothe and capacitancesisset
bytheratioofgate-to-bodyoverlapareatogate-to-drain/source
overlapareaand,bydesign,thegate-to-drainandgate-to-source
overlapsaresmallerthanthegate-to-bodyoverlap.Asshownin
TableI,thetotalcapacitancefromthegatetothesourceortothe
draininourmeasureddevices isroughly40%of
the main actuation capacitance , with this ratio reducing
to 27%inthescaleddevicewithasomewhatimprovedlayout.
Sincetheyarenotnegligible,thedrainandsourceparasiticca-
pacitorsmustbeincludedinboththedelayandenergyanalyses.
Bycombiningtheelectricalandmechanicalmodels,perfor-
manceestimatesofageneralMEM-relaydevicehavebeenob-
tained and verified by experiment [6]. These estimates can in
turnbeusedtopredicttheperformanceofdeviceswithdifferent
dimensions. To expedite circuit design with the relays these
modelshavealsobeenimplementedinVerilog-A.Theperfor-
situationandusingthesevaluesin(6)leadstotherangeofre- manceoftheanalyticalandcomputermodelsiswellcorrelated
sistancesgiveninTableI. withmeasureddataforasimilardevice[8].Notably,thismodel
Theoverallresistanceisalsomodifiedbythesub-1nmthick accuratelycapturesseveralimportantphenomenaofdeviceop-
TiO electrodecoatingthatlimitscurrentflowandmitigatesna- eration: the switching voltages, the mechanical delay, and the
tiveoxide formationto improvedevicereliability [8].Devices electricaldelay.
withthiscoatinghavebeenoperatedforover60billioncycles
andshownosurfacewearafterthiscycling[5],[8].Theresis- III. MEM-RELAYCIRCUITS
tance of this oxide coating is included in the model by com-
Although the previously described models are valuable for
paringmeasureddeviceresistancetothetheoreticalcontactre-
predicting the behavior of MEM-relay circuits, experimental
sistance model introduced above and the results are noted in
verification of their functionality is clearly needed. Previous
Table I.
work has characterized a complementary MEM-relay inverter
Finally,theelectricaldelayisalsodeterminedbytheloadca-
[5],butinordertodemonstratethefeasibilityofimplementing
pacitanceseenbythedevice.InourintendedVLSIapplications
more highly integrated MEM-relay circuits, and to study their
theloadcapacitanceisdominatedbywireparasiticsandtheload
properties,arangeofexamplecircuitshavebeenfabricatedon
presentedbyotherrelaydevices.Theloadpresentedbythede-
vices consists of many parasitic capacitors, but the largest of 1Inaproperlydesigneddevice,thegate-to-bodyandgate-channelcapaci-
thesearethecapacitorsformedbytheairgapbetweenthegate torswilldominatethetotalcapacitanceofthedevice.Ourinitialdevicesuti-
lizedasimplifiedprocessthatrequiredlargeanchorstoensurethattheanchors
and the body across which the device is actuated , and
wouldn’tbereleased,andthustheparallelplatecapacitancefromthegatean-
the parasitic capacitance between the gate and the channel of chorstothesubstratewassignificant.Fortunatelyhowever,thesubstrateplays
the device . The channel terminal of the gate-to-channel essentiallynoroleintheoperationofthedevice,andthusthethicknessofthe
substrateoxidecouldinprinciplebeincreased.Furthermore,inascaledprocess
capacitance is floating when the relay is in the off-state, so it
theanchordimensionscanbedirectlysetbylithographyandhencetheanchor
only contributes to the total capacitance when the relay is in capacitanceofascaleddevicewouldbenegligible.
312 IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.46,NO.1,JANUARY2011
Fig. 4. MEM relay based inverter and measured VTC illustrating full-rail
swingattheoutputanddigitalgain.
Fig.3. Diephotowithrelay-based,propagate-generate-killcircuitshownin
inset.
ademonstrationchip(Fig.3)usinga1 mlithographicprocess
[7].Inthissectionweshowmeasurementsofcircuitscomposed
onlyofrelayswithgroundedbodyterminals,whichlimitedthe
numberofparasiticeffectsthatcouldaffectdeviceoperation.
The static switching characteristics of a MEM relay-based
logicgatearedemonstratedinFig.4,whichshowstheschematic
andmeasuredvoltagetransfercharacteristic(VTC)ofapass-gate
styleMEMinverter/XOR.TheVTCoftheXORwithoneinput
held static at 10 V highlights the expected hysteresis of the
relay-based XOR; this hysteresis window determines the min-
imumvoltageswingrequiredtoswitchbothdevicesonandoff.
The switching voltages of the inverter depend on the pull-in
voltageofthedevicesandthereissomedevice-to-devicepull-in
voltagevariabilityonthetestchip;thisvariabilitywascausedby
anunevenfilmdepositionduringthemanufacturingprocess.This
isevidencedbythedifferenceinthemagnitudeoftheswitching
voltageintheApull-inand (10VminustheAvoltage)pull-in Fig.5. Latchcomposedof MEMrelaydevicesandwaveformsshowingits
operation.FunctionalityofthelatchillustratesthatMEMrelaylogicstagesare
paths.UnlikeCMOS,theconductionoftheMEMrelayisideally composable.
independentofthedrainandsourcevoltages,whichenablesthe
“NMOS”-style pass-gate to swing full-rail at the output. This
VTC shows that the gate is capable of driving the necessary Themostsignificantrelaycharacteristic,aspredictedbythe
output voltages to overcome its own hysteresis window and modelaswellasearlierworks,isalargediscrepancybetween
switchanothergate.LikeinCMOS,thisisacriticalrequirement the intrinsic mechanical and electrical delays of a MEM relay
toenablethecompositionofmultipledigitallogicgates. [6]. These predictions are verified by the measurements in
The composability of MEM-relay circuits is verified in Fig. 6, which show the schematic and two waveforms for a
Fig. 5, where the measured MEM-relay latch demonstrates singlerelaypseudo-NMOSstyleoscillatorthatweremeasured
bothtransparentandopaquestates.LikeinCMOS,acascadeof atthesametimebutatdifferentvoltageresolutions.
twolatchescouldbeusedtocreateaflip-flop.Thelatch’scircuit In Fig. 6, the rising edge is set by the RC time constant of
topology is directly ported from an equivalent pseudo-NMOS the74k externalloadresistorandthecapacitanceduetothe
structure. Although the circuit is functional, it suffers several test infrastructure (probecard and oscilloscope), which is esti-
mechanical delays during operation—i.e., the performance of matedtobe55pF.Themechanicaldelayofthedevicecanbe
this implementation is much worse than it would be if it were measuredfromthetimetherisingedgereachesthepreviously
re-optimizedforthecharacteristicsofMEMrelays. characterized tothetimewhentherelayactuates—i.e.,when
SPENCERetal.:DEMONSTRATIONOFINTEGRATEDMICRO-ELECTRO-MECHANICALRELAYCIRCUITS 313
Fig.7. CMOStoMEMrelaylogicmapping.
marginforcontactresistancevariationwithoutdramaticallyim-
pacting the dynamic device performance. This flexibility may
evenbeexploitedtoenablematerialtradeoffsthatsacrificethe
electrical delay by introducing a slightly higher contact resis-
tanceforimprovedreliability,suchasthepreviouslydescribed
oxidecoating.
Theimbalancebetweenelectricalandmechanicaldelayssug-
Fig.6. Twowaveformsfromasingle-stage,MEMrelay-basedoscillatorthat gests that optimized relay-based circuit designs should mini-
werecollectedatthesametimebutattwodifferentvoltageresolutions,onefor mize the impact of the mechanical delay by arranging all me-
full-scalewaveformsandoneforaprecisetimingmeasurement.Thesewave-
chanical movement to happen simultaneously within each cir-
formscanbeusedtoestimateloadcapacitance(55pF),deviceon-resistance
((cid:0)1k(cid:0)),anddevicemechanicaldelay(34(cid:0)s). cuit.Theresultingdesignparadigm,asshowninFig.7,isthat
MEM relay logic should be designed as single complex gates
wherever possible [6]. Only once the complexity of the logic
theoutputvoltagebeginstodrop.Here,die-to-dievariabilityre- gatehasgrowntotheextentthattheelectricaldelayduetode-
sulted in a lower pull-in voltage than the previously measured vicestackingbecomeslargerthanthemechanicaldelayshould
inverter.Despitethelowerpull-involtage,8Vofgate-to-body the gatebe partitionedintomultiplestages.Therefore,regard-
potentialfortheoscillatordeviceisarelativelylow“gateover- lessofthefinaloutputload,theworstcaseelectricaldelayfor
drive” (i.e., ). When the gate overdriveis lowthe me- a logic stage should be roughly balanced with the mechanical
chanical delay is especially sensitive to changes in the over- delay. For reference, this balance is achieved with a stack of
drive,andthusthemeasuredmechanicaldelayvariesbetween 600 relays when driving a single device (fanout of one) using
– sondifferentcycles. thecurrentlyfabricateddevices.Astackof290relaysbalances
Oncetherelayactuates,theoutputisdischargedbasedonthe thedelayswhenusingthescaleddevicesdescribedlaterinthis
electricaldelayoftheMEMrelay.Theoscillator’sfallingedge work.
seesthesameloadcapacitanceastherisingedge,butitsdelayis This design paradigm is demonstrated in the carry-genera-
setbytheon-resistanceoftherelay,whichisestimatedas1k tioncircuitshowninFig.8.Thiscircuitisakeycomponentof
based on the sub-300 ns electrical delay. The electrical delay the Manchester carry chain adder, which is particularly favor-
measurementinFig.6doesnotreflecttheintrinsicdelayofthe able to MEM relays since the carry signal does not incur ad-
device because of the parasitic capacitances due to the testing ditionalmechanicaldelaysasitpropagatesthrougheachadder
infrastructure.Ifthe actualload capacitancewasonlythe gate stage.Inprinciple,theXORfunctioncanbeimplementedeffi-
of another relay, which is estimated as 300 fF, the resulting cientlyusingasingleMEMrelaywiththeinputsignalstiedto
electricaltimeconstantwouldbeontheorderof 0.3ns. gateandbodyterminals[6],butbecauseonlydeviceswiththe
Even with the high capacitance of the probe card and os- body terminal tied to ground were measured on this test chip,
cilloscope, these measurements indicate that there is at least thepropagateXORisimplementedwithfourdevices[7].The
a difference of several orders of magnitude between the de- waveformsinFig.8also illustratetheoperationofthis circuit
vice’smechanicalandelectricaldelays,whichhasimplications inpropagate,generate,andcarrymodes,showingthatMEMre-
for both the device fabrication and circuit design. Despite the laysareamenabletologicimplementedusingcomplexgates.
manysourcesofcontactresistancediscussedinSectionII,the Given its immeasurably low leakage current [4] (and hence
relatively small electrical delay means that there is significant thepotentialforverylarge retentiontimes),the MEMrelayis
314 IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.46,NO.1,JANUARY2011
Fig.8. MEMrelaybasedcarrygenerationcircuitandmeasuredwaveformdemonstratingoperationinpropagate,generateandkillmodes.
alsoverywellsuitedforimplementingDRAMs.Thestructure
of this circuit is illustrated in Fig. 9, which shows a 10-bit
DRAM column composed of MEM relays constructed in a
NAND configuration. Each DRAM cell consists of three de-
vicesasseeninFig.9:astoragedevicewhichcaneithershort
or open the read bit-line , an access device that gates
the signal between the write bit-line and the gate of
the storage device, and a bypass device thatis in parallel with
thestoragedeviceandalsoattachedtothereadbit-line.
During a read operation, the read bit-line output is pre-dis-
charged to a low voltage and the read word-line of the cell
being interrogated is lowered from its normally
highvoltage.Becausethereadword-lineisnormallyhigh,the
bypass devices in every cell except for the cell being read are
turned on, shunting/bypassing the corresponding storage de-
vices.Thus,ifthegatecapacitanceofthestoragedeviceinthe
interrogatedcellcontainsenoughchargesothatdevicewillbe
turnedon,aconducting pathfrom thesupply tothebottomof
Fig. 9. Read and write of a single bit in a MEM-relay-based NAND-style
thereadbit-linestackwillbeformedand willbepulled DRAM column. The (cid:0)(cid:2) (cid:3)(cid:4)(cid:5) to (cid:0)(cid:2) (cid:3)(cid:6)(cid:5) signals are high so that the
high.Otherwise, willremainlow.Duringawriteopera- highlighteddevicesattachedtothemareturnedon,creatingaconductivepath
from(cid:7) tothetenthDRAMcell.
tion israisedhightoallow tochargeordis-
chargethegateofthestoragedevice.
Thisconfigurationallowsthememorytoperformareadop-
a100k pull-downresistorthatbypassedthepull-downrelay
eration in a single mechanical turn-on delay (for decoding the
inordertoreducethenumberofcontrolsignalsneededtotest
address) plus a mechanical turn-off delay (to turn off the by-
the circuit as well as enable the simultaneous read and write
pass device of the cell being read). As previously mentioned,
operation.
theturn-offdelayismuchsmallerthanturn-ondelay,andhence
Finally,thefactthateachofthecircuitsdescribedwereable
thereadlatencyofthisDRAMdesignissubstantiallylowerthan
todrivetheprobecardandtheoscilloscopesuggeststhatthede-
designssimilartoCMOSimplementationsthatwouldrequire2
vicesare capableofdrivinglarge capacitiveloads.Theability
ormoreturn-ondelays.
todrivetheseloadspresentstheMEMrelayasacandidatefor
An experiment illustrating the operation of the DRAM is
anI/Odevice.Fig.10demonstratestheMEMrelayinthatrole
shown in Fig. 9, where the waveforms show a simultaneous
by showing the operation of a 2-bit thermometer-coded DAC.
memory read and write. The 10-bit memory cell was fully
TheDACisimplementedusingthreeMEMrelay-basedbuffers
integratedexceptfor(duetolackofvias)thewiresbetweenthe
which create a programmable resistor divider between the I/O
drain of the access device and the gate of the storage device.2
voltagerailandground.Notethatbecauserelayactuationide-
Thepre-dischargeofthereadbitlinewasaccomplishedusing
ally depends only on the gate-to-body voltage and not on the
2Thisexternalconnectionmeantthatthestoragenodeofthedevicewasex- drainorsourcevoltages,itisrelativelystraightforwardtoincor-
posedtothecapacitanceandleakageoftheprobecardandexternalwires.Ac- porate a level-shiftinto the output stage. This is demonstrated
curatemeasurementsoftheretentiontimeoftheDRAMcouldthereforenotbe
inFig.10,wheretheoutputfull-scalevoltageis3Vwhilethe
takensincethemeasuredretentiontimewouldbecompletelysetbyexternal
leakagecurrentdischargingtheexternalcapacitance. relayactuationvoltageis10V.
SPENCERetal.:DEMONSTRATIONOFINTEGRATEDMICRO-ELECTRO-MECHANICALRELAYCIRCUITS 315
Fig.10. AMEMrelaybased2-bitthermometercodedDAC.Theoutputsfor“11X”and“00X”inputsareshown,whereX=(cid:0) .Alevelshiftisbuiltintothe
DACbecausethe(cid:0) voltageisdifferentthantheactuationvoltage.
IV. EFFECTSOFSCALINGMEMRELAYS of a small number of bonds; given five bonds, each of which
haveanenergyof 0.2aJ[14],theminimumswitchingenergy
Even though the previously described circuits demonstrate
would be 4 aJ per device switching cycle [8]. This is roughly
the functionality of MEM relay-based circuits, the size and
a factor of ten lower than the minimum energy per switching
high switching voltages of the current devices do not imme-
cycleofasingle,minimum-sized65nmCMOStransistor[2],
diately demonstrate the benefits of these MEM circuits over
[8].Itisimportanttore-iteratehoweverthatsincerelay-based
currentCMOSimplementations.However,likeCMOStransis-
circuits will be constructed in a significantly different manner
tors, MEM relays are expected to achieve substantially lower
thantheirCMOScounter-parts,thetrueenergybenefitofrelays
switchingenergyandlowerdelayastheirphysicaldimensions
mustbeevaluatedatthecircuitlevel.
are scaled.
The modifications to the device necessary to achieve these
benefits can be analyzed by looking at the sources of energy V. COMPARISONOFSCALEDMEM-RELAYANDCMOSLOGIC
consumptioninaMEMrelay.Energyisprimarilyspentdriving TorealisticallyprojectthebenefitsofaMEMrelayitisnec-
the parasitic capacitances, and thus the energy/per operation essary to compare modern CMOS circuits against their coun-
is improved by decreasing the load capacitance—achieved by terparts built from scaled versions of fabricated MEM relays.
reducing the actuation area—and lowering the relay operating However, in measuring the original test chip, several parasitic
voltage.Bothoftheseeffectsreducetheelectricalforceavailable effects that affected the operation of the devices were discov-
to actuate the device, and hence a corresponding decrease in ered.Specifically,therelativelylargegate-to-drainandgate-to-
the spring constant—achieved by thinning the flexures—and source capacitances lead to parasitic actuation forces between
reductionofthegapthicknessisnecessarytoreducethepull-in thesourceordrainelectrodesandthegate.Throughthismech-
voltage.Eventhoughthepull-involtageandappliedforcearere- anismthevoltageonthesourceanddrain(relativetothegate)
duced,themassofthedevicescalesmorequicklythanthespring couldchangethepull-involtage,asseeninFig.11(a).
constant,whichresultsinfasteractuationatsmallerdimensions. In addition to the parasitic effects caused by the drain and
Ofcourse,thisimprovedperformanceandparticularlythere- source-to-gate overlaps, the overlap between the channel and
duction in energy cannot be extended forever. Ultimately, the thebodycouldresultinanelectrostaticattractiveforcebetween
spring must be able to restore the relay to its un-actuated po- thechannelandthebody.Ifthisforceissufficientlylarge,itmay
sition after the electrical force is removed. The surface forces keepthedeviceintheonstateafterthegate-to-bodyvoltageis
holding the relay in place—primarily hydrogen bonds, capil- removed.Thecombinationoftheseeffectsmadetheuseofthe
laryforces,andVanderWaalsforce[13]—thereforeprovidea bodyelectrodefordevicecontrolunpredictable.Theseundesir-
lowerboundonthestrengthofthespringandsettheminimum ableeffectsmustbeeliminatedinapracticalscaleddevice,and
amountofenergyforswitchingthedeviceonandoff.Forlarge asafirststepinthatprocess,deviceswithanimprovedlayout
contact dimple areas, these forces are proportional to the area were fabricated and tested. Fig. 12 shows an image of the de-
of the contact dimple.Thus, eventhough the springforcewill vices[15]andofthetestchiputilizingthesedevices.Inthesede-
become weaker as the device is scaled, scaling the contact di- vicesthedrainandsourceareaswerereduced,thechannelsize
mensionswillallowthespringforcetodominatesurfaceforces was minimized, and the channel-to-body overlap was shrunk.
evenasthedevicebecomessmaller. Thesechangesresultedinadrasticreductioninparasiticcapac-
However, eventually both the surface forces and contact itancesandforcesasevidencedbyFig.11(b).
resistance will be determined by a handful of bonds between Utilizingtheimproveddevicedesign,aone-bitadderwasim-
thechannelandthedrain/sourceelectrode.Atthispoint,further plementedonthesecondtestchipinastylethattookadvantage
scaling of the contact dimple area leaves the surface forces oftheabilitytousebothgateandbodyaslogicinputs.Asshown
largely unchanged[13].Thisimplies thatthe minimum stored inFig.13,sincetherelayisactuatedwhentheabsolutevalueof
spring energy must be large enough to overcome the energy gatepotentialisgreaterthanthepull-involtage,itispossibleto
316 IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.46,NO.1,JANUARY2011
Fig.11. Dependenceofpull-inandreleasevoltages(whicharemeasuredbetweengateandbody)onthedraintobodyvoltageof(a)theoriginaldevicedesign,
and(b)thereviseddesignwithreducedsource/draintogateoverlap.
Fig.13. Schematicandmeasuredwaveformsofaone-bitadderimplemented
usingtherevisedlayoutfortheMEMrelays.3
optimizationsareincorporatedintothedevicelayouttomaximize
areaefficiencyandminimizeparasiticcapacitances.Specifically,
the device anchors were moved in line with the flexures, the
flexures were adjusted so that they contact the top/bottom of
the actuation arearather than the sides, the actuation area was
extendedacrosstheentirelengthofthedevice,andthelengthof
Fig. 12. Die photo of the test chip using the revised device layout and a
thechannelwasminimizedbyextendingthedrainandsource.
zoomed-inimageofasingledevice.
Thefirstthreeoftheseoptimizationsreducetheoverallfootprint
byenablingtheactuationareatobeincreasedwithoutstretching
usetheback-gateasaninputtoimplementtheXORoftwosig- The improved device layout from this second test chip was
nals (for both the propagate and sum calculations) rather than usedasthestartingpointforthedesignofascaleddeviceused
thefour-deviceXORusedontheoriginaltestchip.Sumisim- to analyze MEM relay logic performance. Fig. 14 presents a
plementedasawired-XORgateandbothtrueandcomplement device layout optimized for a 90 nm equivalent MEM relay
versionsofthecarrysignalarecomputedtoavoidtheadditional technology;inthis devicemost dimensionsaredirectlyscaled
mechanicaldelaythatmightberequiredtoinverttheincoming by a factor of 50 compared to the measured devices. the de-
carrysignal. vice footprint vertically, while the fourth minimized the load
Fig.13alsoshowsthemeasuredresultsfromthisfull-adder capacitancebylimitingthechanneloverlaparea.
circuit. The operating voltage used in these results was higher Though better performance, energy, and/or area could
than on the previous demonstration chip because the as-fabri- possibly be achieved by more radical changes in the device
catedgapthicknesswaslargerthanexpected,raisingthepull-in
3Thesumandcarry-outsignalsdon’tpreciselytrackthecarry-insignalin
voltage of the device. We expect that this thickness would be themeasuredwaveformsbecauseofasourceresistancethatwasattachedtothe
bettercontrolledinanindustrialfabricationfacility. supplygenerating(cid:0) inordertolimitthecurrenttothedevices.Thissourcere-
sistanceformedaresistivedividerwiththeresistanceoftheoscilloscopeprobe.
In an effort to reduce the footprint of the device while pre- (cid:0) wasmeasuredonthesourcesideofthesourceresistanceandthusdidnot
servingtheoriginaldevicetopology,anumberofevolutionary seethesamevoltagedivisionasSand(cid:0) .
SPENCERetal.:DEMONSTRATIONOFINTEGRATEDMICRO-ELECTRO-MECHANICALRELAYCIRCUITS 317
Fig.15. Schematicofa32-bitManchestercarrychainadderusingafulladder
cellimplementedasasinglecompoundgatebuiltfromMEMrelays.
Fig.14. Possiblelayoutfora90nmtechnologyMEMrelaythatincorporates
optimizationstoimproveareaefficiencyandreduceparasiticcapacitance. functioninonecompoundgateandrequires384relays,eachof
which occupies slightly less than 12 m . Assuming a wiring
structure(e.g.,byswitchingtothesimplecantileversanalyzed overhead of 30%, this results in a total area of 7000 m
in[6]),thisscaledversionofthefabricateddevicesisanalyzed fortheMEM-relayadder.
because of the similarities with the current devices that have In order to benchmark the NEM relay-based adder, it was
already achievedgoodyieldand reliabilityandare thuscloser compared to a 32-bit CMOS Sklansky adder [17]. Sklansky
to large-scale realization. To be more specific, although the adderswereidentifiedastheminimumenergytopologyacross
number of devices fabricated was insufficient for a thorough a wide range of delays in [16]. At the minimum energy/max-
statisticalstudy,allofthedevicesthatweretestedonthefabri- imum delay, the adder uses 836 gates and occupies an area of
cated chips were functional, and as mentioned previously, the 2000 m whenplacedandroutedusingstandardcellswith
devicesremainedfunctionalaftermorethan60billioncycles. no delay constraint. The energy per operation of the CMOS
TableIshowstheconsequencesofthisscalingonthedevice adderisbasedupontheresultsfrom[16],andVerilog-Asimula-
parametersthatdirectlyimpactrelayperformance.Thevaluesin tionsofthewholerelayadderwereusedtoestimateitsenergy.
thetablearecalculatedbyusingthepreviouslyestablishedelec- Fig. 16 shows the energy-delay tradeoffs in CMOS and
tricalandmechanicalmodelsalongwiththenewdevicedimen- MEM-relay adders where the adders have been designed to
sions.ItisimportanttonoticethattheswitchingdelayofaMEM drivealoadcapacitanceofeither25fFor100fF.InFig.16(a)
relayisdominatedbythemechanicaldelayofthestructureeven theenergyspentdrivingtheloadisomittedinordertofacilitate
atthesescaleddimensions.Specifically,asseeninTableI,the comparisonsbetweenonlytheadders,whileFig.16(b)includes
mechanicaldelayisontheorderoftensofnanoseconds,while theloadenergytocomparetheoverallperformance.Thedelay
the intrinsic electrical delay of the device is less than five pi- of all of the adders includes the effects of driving the load
coseconds.Thisremainstrueevenforstacksof32seriesrelays capacitanceateachoftheiroutputs.
aslongasthecontactresistanceislessthan15k ,andhence Thedelayfromdrivingtheseloadcapacitancesincreaseswith
theprecisescalingbehaviorofthecontactresistanceisunlikely thesizeoftheload.Whentheelectricaldelaybecomescompa-
toaffectthedesignstyleofthecircuit. rabletothemechanicaldelay,itisbeneficialtoaddabuffering
In order to illustrate the potential benefits of scaled MEM stagetodrivetheloadandreducetheelectricaldelayofthecir-
relays while keeping in mind the differences in circuit design cuit.Consequently,theresultsforrelayadderswith100fFload
paradigms, we next compare the energy-performance charac- inFig.16assumeasinglebufferisaddedattheoutputtodrive
teristicsofanoptimized32-bitMEMrelay-basedadderagainst the loads. This modification roughly doubles the delay of the
thoseofanoptimizedCMOSimplementation[16].Theimple- unloaded circuit because two mechanical delays are incurred,
mentationofthe32-bitrelayadder(whichutilizesthefull-adder butessentiallyeliminatestheelectricaldelayandthusimproves
cellsmeasuredinFig.13)isshowninFig.15.Notethatintotal, performanceinthemostenergy-efficientway.
only12relays(ascomparedto24transistorsinCMOS)areused TheenergyoftheCMOSadderreachesitsminimumenergy
toimplementafull-addercell,whichhelpstoamortizethearea point [1], [16] for delays above ns. Thus, at delays of
penaltystemmingfromthefactthateachindividualMEMrelay ns,asingleMEM-relayadderwouldofferanimprovement
issignificantlylargerthanaminimum-sizedCMOStransistor. of or more in energy efficiency with an additional area
Inordertoimplementthecompletemulti-bitadder,theMEM overheadof comparedtotheCMOSadder.Applications
relay-based full-adder cell is used in a ripple-carry configura- requiringthroughputsof MOPSorlesswouldimmediately
tion. Overall, the structure implements a complete 32-bit add benefitfromdeploymentofsuchatechnology.