Table Of ContentMehdi Dehbashi · Görschwin Fey
Debug
Automation from
Pre-Silicon to
Post-Silicon
Debug Automation from Pre-Silicon to Post-Silicon
Mehdi Dehbashi • Görschwin Fey
Debug Automation
from Pre-Silicon
to Post-Silicon
123
MehdiDehbashi GörschwinFey
InstituteofComputerScience InstituteofSpaceSystems
UniversityofBremen GermanAerospaceCenter
Bremen,Germany Bremen,Germany
ISBN978-3-319-09308-6 ISBN978-3-319-09309-3(eBook)
DOI10.1007/978-3-319-09309-3
SpringerChamHeidelbergNewYorkDordrechtLondon
LibraryofCongressControlNumber:2014948782
©SpringerInternationalPublishingSwitzerland2015
Thisworkissubjecttocopyright.AllrightsarereservedbythePublisher,whetherthewholeorpartof
thematerialisconcerned,specificallytherightsoftranslation,reprinting,reuseofillustrations,recitation,
broadcasting,reproductiononmicrofilmsorinanyotherphysicalway,andtransmissionorinformation
storageandretrieval,electronicadaptation,computersoftware,orbysimilarordissimilarmethodology
nowknownorhereafterdeveloped.Exemptedfromthislegalreservationarebriefexcerptsinconnection
with reviews or scholarly analysis or material supplied specifically for the purpose of being entered
and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of
this publication or parts thereof is permitted only under the provisions of the Copyright Law of the
Publisher’slocation,initscurrentversion,andpermissionforusemustalwaysbeobtainedfromSpringer.
PermissionsforusemaybeobtainedthroughRightsLinkattheCopyrightClearanceCenter.Violations
areliabletoprosecutionundertherespectiveCopyrightLaw.
Theuseofgeneraldescriptivenames,registerednames,trademarks,servicemarks,etc.inthispublication
doesnotimply,evenintheabsenceofaspecificstatement,thatsuchnamesareexemptfromtherelevant
protectivelawsandregulationsandthereforefreeforgeneraluse.
While the advice and information in this book are believed to be true and accurate at the date of
publication,neithertheauthorsnortheeditorsnorthepublishercanacceptanylegalresponsibilityfor
anyerrorsoromissionsthatmaybemade.Thepublishermakesnowarranty,expressorimplied,with
respecttothematerialcontainedherein.
Printedonacid-freepaper
SpringerispartofSpringerScience+BusinessMedia(www.springer.com)
Preface
TheapplicationofVeryLargeScaleIntegration(VLSI)circuitsisubiquitouswhile
thesizeofthehardwarecomponentsisshrinking.VLSIcircuitsareusedforawide
range of different applications in embedded systems such as medical electronics,
automotive systems and avionics. A failure of a chip in non-critical applications
maycausesignificanteconomiclosswhileincriticalapplicationsmayalsoendanger
human’slivesintheworstcase.Consequently,thecorrectdesignofVLSIcircuits
iscrucial.
Thedebuggingprocessisdedicatedtolocalizeandtorectifytherootcauseofthe
erroneous behavior of VLSI circuits. This process often remains as a manual task
andincreasesthetimerequiredfordevelopmentcyclesofIntegratedCircuits(ICs)
significantly. Therefore, debug automation procedures are required to accelerate
finding and fixing bugs and faults and, consequently, to increase the productivity
ofICdesign.
This book contributes to debugging and diagnosis technology at the most
challenging gaps on different abstraction levels of a hardware system, i.e., chip,
gate-level,RegisterTransferLevel(RTL)andtransaction-level.
In this book, we propose automated debugging approaches for the bugs and
the faults which appear in different abstraction levels of a hardware system, i.e.,
transaction-level,RTL,andgate-level.Ourautomateddebugapproachesareapplied
toahardwaresystematdifferentgranularitiestofindthepossiblelocationofbugs
andfaults.Thetransaction-baseddebugapproachisappliedtoahardwaresystemat
transaction-levelassertingthecorrectrelationoftransactions.Ourautomateddebug
approachfordesignbugsfindsthepotentialfaultcandidatesatRTLandgate-level
ofacircuit.Inthiscase,logicbugsandsynchronizationbugsareconsideredasthey
are the most difficult bugs to be localized. For electrical faults and, in particular,
delayfaultsourproposeddebugautomationfindsthepotentialfailingspeedpathsin
acircuitatgate-level.
Theproposeddebugapproachesfortransactions,designbugsandelectricalfaults
have been evaluated on suitable benchmarks at different levels of abstraction, i.e.,
transaction-level,RTLandgate-level.Theexperimentshaveshownthatourdebug
v
vi Preface
approaches achieve high diagnosis accuracy and reduce the debugging time. As a
result, the time of the IC development cycle decreases and the productivity of IC
designincreases.
We would like to thank all our coauthors for the fruitful collaboration. In
particular,wewouldliketothankDr.AndréSülflowfortheconstructivediscussions
andhissupportduringourworkonthisbookandtheunderlyingtechniques.Weare
gratefultoProf.KaushikRoyandProf.AnandRaghunathanfortheircollaboration,
importantdiscussions,andcomments.WewouldliketothanktheGermanResearch
Foundation(DFG)forfundingourwork.
Munich,Germany MehdiDehbashi
Bremen,Germany GörschwinFey
June2014
Contents
1 Introduction ................................................................ 1
1.1 PartI:DebugofDesignBugs......................................... 7
1.2 PartII:DebugofDelayFaults ........................................ 8
1.3 PartIII:DebugofTransactions ....................................... 8
2 Preliminaries ............................................................... 9
2.1 CircuitsandSensitizedPaths.......................................... 9
2.2 ConjunctiveNormalForm ............................................ 11
2.3 Three-ValuedLogicinBooleanSatisfiability........................ 13
2.4 Model-BasedDiagnosis............................................... 13
2.4.1 SAT-BasedDebugging........................................ 14
2.5 Transaction-BasedDebug............................................. 19
2.5.1 Transaction .................................................... 19
2.5.2 TransactionDebugPatternSpecificationLanguage......... 20
2.6 OverviewofBenchmarks ............................................. 23
PartI DebugofDesignBugs
3 AutomatedDebuggingforLogicBugs ................................... 27
3.1 IntegrationofFormalDebuggingwithTestbench-Based
Verification............................................................. 29
3.2 CounterexampleVersusFaultCandidate............................. 30
3.3 LocalBranchActivation .............................................. 31
3.3.1 BranchandPathActivation................................... 32
3.3.2 LBAAlgorithm................................................ 33
3.4 MinimizationofSensitizedPathIntersection ........................ 36
3.5 LimitedMinimizationFollowedbyBranchActivation.............. 41
3.6 ExperimentalResults.................................................. 42
3.7 Summary............................................................... 48
vii
viii Contents
4 AutomatedDebuggingfromPre-SilicontoPost-Silicon ............... 49
4.1 HardwareStructuresforPost-SiliconDebugging.................... 50
4.2 GeneralizedAutomatedDebuggingProcedure ...................... 52
4.3 AutomatedPost-SiliconDebugging .................................. 54
4.3.1 Case1:DesignBug ........................................... 55
4.3.2 Case2:ElectricalFault........................................ 55
4.3.3 Case3:ElectricalFaultandDesignBug..................... 56
4.3.4 Case4:IndefiniteCase........................................ 56
4.4 InstantiationoftheGeneralizedDebugFlowforDesignBugs...... 57
4.5 ExperimentalResults.................................................. 57
4.6 Summary............................................................... 60
5 AutomatedDebuggingforSynchronization
Bugs ......................................................................... 63
5.1 SynchronizationBugModel .......................................... 64
5.2 Approach............................................................... 65
5.3 SynchronizationCorrectionBlock.................................... 68
5.4 Algorithm .............................................................. 71
5.5 ExperimentalResults.................................................. 72
5.6 Summary............................................................... 76
PartII DebugofDelayFaults
6 AnalyzingTimingVariations ............................................. 79
6.1 TimingParameters..................................................... 81
6.2 Approach............................................................... 82
6.2.1 TAMEngine................................................... 83
6.2.2 TimeControlandVariationControl.......................... 87
6.2.3 SlowdownVersusSpeedup ................................... 89
6.3 PropertiesofTAM..................................................... 91
6.4 ExperimentalResults.................................................. 95
6.5 Summary............................................................... 99
7 AutomatedDebuggingforTimingVariations .......................... 101
7.1 SpeedpathDebugging ................................................. 102
7.2 FaultModel............................................................ 103
7.2.1 SlowdownFaultModel ....................................... 103
7.2.2 SpeedupFaultModel.......................................... 103
7.2.3 SlowdownandSpeedupFaultModel......................... 104
7.3 Approach............................................................... 105
7.4 TAM-BasedDebugging ............................................... 107
7.4.1 Algorithm...................................................... 108
7.5 ExperimentalResults.................................................. 109
7.6 Summary............................................................... 113
Contents ix
8 EfficientAutomatedSpeedpathDebugging ............................. 115
8.1 Approach............................................................... 116
8.2 STA-BasedDebugging................................................ 117
8.2.1 OverclockingVersusTimingVariation....................... 117
8.2.2 DebuggingModel ............................................. 121
8.2.3 InstanceCreationAlgorithm.................................. 124
8.3 ExperimentalResults.................................................. 127
8.4 Summary............................................................... 128
PartIII DebugofTransactions
9 OnlineDebugforNoC-BasedMultiprocessorSoCs ................... 133
9.1 Approach............................................................... 135
9.1.1 Monitor ........................................................ 137
9.1.2 DebugRedundantInformation ............................... 138
9.1.3 DebugUnit .................................................... 139
9.1.4 TransactionOrdering.......................................... 141
9.1.5 Filter ........................................................... 142
9.1.6 DebugFSM.................................................... 143
9.1.7 DesignDecisionsandLimitations............................ 145
9.2 DebugFlow............................................................ 146
9.3 ExperimentalResults.................................................. 148
9.3.1 DebugPatternforRace ....................................... 149
9.3.2 DebugPatternforDeadlock .................................. 152
9.3.3 DebugPatternforLivelock ................................... 155
9.3.4 OverheadandSimulationResults ............................ 156
9.4 Summary............................................................... 157
10 SummaryandOutlook .................................................... 159
References......................................................................... 161
Index............................................................................... 169
