Data Management on New Hardware: 7th International Workshop on Accelerating Data Analysis and Data Management Systems Using Modern Processor and Storage Architectures, ADMS 2016 and 4th International Workshop on In-Memory Data Management and Analytics, IM

174 Pages·2017·10.98 MB·English

by  Spyros Blanas

Spyros Blanas
Rajesh Bordawekar
Tirthankar Lahiri
Justin Levandoski
Andrew Pavlo (Eds.)
5
9 Data Management
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on New Hardware
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7th International Workshop on Accelerating
Data Analysis and Data Management Systems Using
Modern Processor and Storage Architectures, ADMS 2016
and 4th International Workshop on In-Memory Data
Management and Analytics, IMDM 2016
New Delhi, India, September 1, 2016, Revised Selected Papers
123
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Spyros Blanas Rajesh Bordawekar
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Tirthankar Lahiri Justin Levandoski
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Andrew Pavlo (Eds.)
Data Management
on New Hardware
7th International Workshop on Accelerating
Data Analysis and Data Management Systems Using
Modern Processor and Storage Architectures, ADMS 2016
and 4th International Workshop on In-Memory Data
Management and Analytics, IMDM 2016
New Delhi, India, September 1, 2016
Revised Selected Papers
123
Editors
SpyrosBlanas JustinLevandoski
OhioState University Microsoft Corporation
Columbus, OH Redmond, WA
USA USA
RajeshBordawekar AndrewPavlo
IBMThomas JWatson Research Center Computer Science Department
Yorktown Heights, NY Carnegie MellonUniversity
USA Pittsburgh, PA
USA
Tirthankar Lahiri
Oracle Cor.
RedwoodShores, CA
USA
ISSN 0302-9743 ISSN 1611-3349 (electronic)
Lecture Notesin Computer Science
ISBN 978-3-319-56110-3 ISBN978-3-319-56111-0 (eBook)
DOI 10.1007/978-3-319-56111-0
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Preface
TheInternationalWorkshoponAcceleratingAnalyticsandDataManagementSystems
Using Modern Processor and Storage Architectures (ADMS) and the International
Workshop on In-Memory Data Management (IMDM) were held jointly this year.
The objective of this workshop is to investigate opportunities in accelerating
analytics/data management systems and workloads (which include traditional OLTP,
datawarehousing/OLAP,ETL,streaming/real-time,businessanalytics,andXML/RDF
processing)runninginmemory-onlyenvironments,usingprocessors(e.g.,commodity
and specialized multi-core, GPUs, and FPGAs), storage systems (e.g., storage-class
memories like SSDs and phase-change memory), and hybrid programming models
suchasCUDA,OpenCL,andOpenACC.Theworkshophopestoexploretheinterplay
between overall system design, core algorithms, query optimization strategies, pro-
gramming approaches, as well as performance modeling and evaluation, from the
perspective of data management applications.
Inaddition,overthepast30years,memorypriceshavebeendroppingbyafactorof
10every5years.Mainmemoryisthe“newdisk”fordatastorage.ThenumberofI/O
operationspersecond(IOPS)inDRAMisfargreaterthanotherstoragemediasuchas
harddisksandSSDs.DRAMisreadilyavailableinthemarketatabetterpricepointin
comparisonwithDRAMalternatives.ThesetrendsmakeDRAMabetterstoragemedia
for latency-sensitive database applications, large-scale Web applications, and future
applications such as wearable devices. The International Workshop on In-Memory
Memory Data Management and Analytics (IMDM) aims to bring together researchers
and practitioners interested in the proliferation of in-memory data management and
analytics infrastructures.
Theseproceedings containpapers fromthejoint ADMS/IMDM workshop that was
co-located with VLDB 2016 in New Delhi, India. The workshops were well-attended
and sparked interesting technical discussions.
All papers in these proceedings were peer-reviewed by an expert Program Com-
mittee comprising experts from both industry and academia. We would like to thank
these committee members as well as the authors for contributing high-quality work.
February 2017 Spyros Blanas
Rajesh Bordawekar
Tirthankar Lahiri
Justin Levandoski
Andrew Pavlo
Organization
Workshop Organizers
Spyros Blanas Ohio State University, USA
Rajesh Bordawekar IBM T.J. Watson Research Center, USA
Tirthankar Lahiri Oracle, USA
Justin Levandoski Microsoft Research, USA
Andrew Pavlo Carnegie Mellon University, USA
Program Committee
Reza Azimi Huawei, China
Nipun Agarwal Oracle Labs, USA
Christoph Dubach University of Edinburgh, UK
Qiong Luo Hong Kong University of Science and Technology
(HKUST), Hong Kong
Sina Merji IBM Toronto, Canada
Mohammad Sadoghi IBM T.J. Watson Research, USA
Nadathur Satish Intel, USA
Sudhakar Yalamanchili Georgia Tech, USA
David Schwalb Hasso-Plattner Institute (HPI), Germany
Viktor Rosenfeld TU Berlin, Germany
Shirish Tatikonda Target, USA
Christian Lang Acelot, USA
Vincent Kulandaisamy IBM Analytics, USA
Eric Boutin MemSQL, USA
Badrish Chandramouli Microsoft Research, USA
Martin Grund Amazon, USA
Ryan Johnson LogicBlox, USA
Hideaki Kimura Hewlett Packard Enterprise, USA
Viktor Leis TU Munich, Germany
Ippokratis Pandis Amazon, USA
Evangelia Sitaridi Columbia University, USA
Ryan Stutsman University of Utah, USA
Sandeep Tata Google, USA
Pinar Tozun IBM Research, USA
Oded Shmueli Technion, Israel
Contents
Cache-Sensitive Skip List: Efficient Range Queries on Modern CPUs . . . . . . 1
Stefan Sprenger, Steffen Zeuch, and Ulf Leser
Exploit Every Cycle: Vectorized Time Series Algorithms on Modern
Commodity CPUs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Bo Tang, Man Lung Yiu, Yuhong Li, and Leong Hou U
Compression-AwareIn-MemoryQueryProcessing:Vision,SystemDesign
and Beyond . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Juliana Hildebrandt, Dirk Habich, Patrick Damme,
and Wolfgang Lehner
Overtaking CPU DBMSes with a GPU in Whole-Query Analytic
Processing with Parallelism-Friendly Execution Plan Optimization . . . . . . . . 57
Adnan Agbaria, David Minor, Natan Peterfreund, Eyal Rozenberg,
and Ofer Rosenberg
To Copy or Not to Copy: Making In-Memory Databases Fast
on Modern NICs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Aniraj Kesavan, Robert Ricci, and Ryan Stutsman
DBMS Data Loading: An Analysis on Modern Hardware . . . . . . . . . . . . . . 95
Adam Dziedzic, Manos Karpathiotakis, Ioannis Alagiannis,
Raja Appuswamy, and Anastasia Ailamaki
Locality-Adaptive Parallel Hash Joins Using Hardware
Transactional Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Anil Shanbhag, Holger Pirk, and Sam Madden
SwingDB: An Embedded In-memory DBMS Enabling Instant
Snapshot Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Qingzhong Meng, Xuan Zhou, Shiping Chen, and Shan Wang
Runtime Fragility in Main Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Endre Palatinus and Jens Dittrich
Author Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Cache-Sensitive Skip List:
Efficient Range Queries on Modern CPUs
B
Stefan Sprenger( ), Steffen Zeuch, and Ulf Leser
Institute for Computer Science, Humboldt-Universit¨at zu Berlin,
Unter den Linden 6, 10099 Berlin, Germany
{sprengsz,zeuchste,leser}@informatik.hu-berlin.de
Abstract. Duetoeverfallingpricesandadvancementsinchiptechnolo-
gies, many of today’s databases can be entirely kept in main memory.
However,reusingexistingdisk-basedindexstructuresformanagingdata
inmemoryleadstosuboptimalperformanceduetoinefficientcacheusage
andnegligenceofthecapabilitiesofmodernCPUs.Accordingly,anum-
ber of main-memory optimized index structures have been proposed,
yet most of them focus entirely on single-key lookups, neglecting the
equally important range queries. We present Cache-Sensitive Skip Lists
(CSSL)asanovelindexstructurethatisoptimizedforrangequeriesand
exploitsmodernCPUs.CSSLisbasedonacache-friendlydatalayoutand
traversal algorithm that minimizes cache misses, branch mispredictions,
and allows to exploit SIMD instructions for search. In our experiments,
CSSL’s range query performance surpasses all competitors significantly.
Even for lookups, it is only surpassed by the recently presented ART
indexstructure.WethereforeseeCSSLasaseriousalternativeformixed
key/range workloads on main-memory databases.
· ·
Keywords: Index structures Main-memory databases Scientific
databases
1 Introduction
Over the last years, various index structures were designed for fast and space-
efficient execution of search operations in main memory, like the adaptive radix
tree (ART) [13] or Cache-Sensitive B+-tree (CSB+) [18]. By reducing cache
misses, improving cache line utilization, and exploiting vectorized instructions,
they outperform conventional database index structures, like B-trees [5], which
weremostlydesignedtoreducediskaccesses.Mostofthesenovelindexmethods
focusonsingle-keylookupsandshowsuboptimalperformanceforrangequeries,
despite their importance in many applications. Use cases for range queries are
numerous,suchas:queriesinadatawarehousethataskforsalesinacertainprice
range, analysis of meteorological data that considers certain yearly time periods
in long time series, and Bioinformaticians who build databases of hundreds of
millions of mutations in the human genome that are analyzed by ranges defined
by genes [9].
(cid:2)c SpringerInternationalPublishingAG2017
S.Blanasetal.(Eds.):ADMS2016/IMDM2016,LNCS10195,pp.1–17,2017.
DOI:10.1007/978-3-319-56111-01
2 S. Sprenger et al.
In this paper, we introduce the Cache-Sensitive Skip List (CSSL), a novel
main-memory index structure specifically developed for efficient range queries
on modern CPUs. CSSL is based on skip lists as described in [16], yet uses
a very different memory layout to take maximal advantage of modern CPU
features like CPU-near cache lines, SIMD instructions, and pipelined execution.
Inthiswork,wefocusonreadperformancebutprovideatechniqueforhandling
updates, too. Besides many other use cases, we see CSSL as perfectly suited for
scientificdatabasesthatpreferfastreadsoverfastwritesandneedrangequeries
in many cases. Especially the bioinformatics community, which is confronted
with an exponentially growing amount of genomic data that is mostly analyzed
with range queries to investigate certain genomic regions [20], may benefit from
our approach.
We evaluated CSSL on data sets of various sizes and properties and com-
pared its performance to CSB+-tree [18], ART [13], B+-tree [7], and binary
search on a static array. We also include experiments with real-world data from
the bioinformatics domain to investigate performance on non-synthetic key dis-
tributions. For range queries and mixed workloads, CSSL is consistently faster
than all state-of-the-art approaches, often by an order of magnitude; also its
lookup performance is way ahead of all competitors except ART.
Theremainingpaperisstructuredasfollows.Thenextsectionintroducesskip
lists, the index structure that CSSL is based on. Section3 presents the Cache-
Sensitive Skip List as our main contribution. Section4 describes algorithms for
executing lookups and range queries on CSSL. In Sect.5, we compare CSSL
against other state-of-the-art index structures using synthetic as well as non-
syntheticdata.Section6discussesrelatedwork,andSect.7concludesthispaper.
2 Preliminaries
Skip lists were originally presented as a probabilistic data structure similar to
B-trees[16].Skiplistsconsistofmultiplelanesofkeysorganizedinahierarchical
fashion (see Fig.1). At the highest level of granularity, a skip list contains a
linked list of all keys in sorted order. In addition to this so-called data list, skip
lists maintain fast lanes at different levels. A fast lane at level i contains n∗pi
elementsonaverage,wherenisthenumberofkeystobestoredand0<p<1is
aparameter.Skiplistswereoriginally proposedasprobabilisticdatastructures,
as the elements to be stored in higher lanes are randomly chosen from those
at lower lanes: Every element of fast lane i appears in fast lane i + 1 with
probabilityp.Thisschemeallowsforefficientupdatesandinserts,yetmakesthe
data structure less predictable.
In our work, we use a deterministic variant of skip lists, so-called perfectly
balanced skip lists [15].Inbalancedskiplists,thefastlaneatleveli+1contains
every 1/p’th element of the fast lane at level i. Accordingly, for p = 0.5 a lane
at level i+1 contains every second element of level i, in which case a skip list
resemblesabalancedbinarysearchtree.Figure1showsabalancedskiplistover
nine integer keys with two fast lanes for p=0.5.