Data converters, phase-locked loops, and their applications

507 Pages·2019·18.81 MB·English

by  Ndjountche

CMOS Analog Integrated Circuits
Data Converters,
Phase-Locked Loops,
and Their Applications

CMOS Analog Integrated Circuits
Data Converters,
Phase-Locked Loops,
and Their Applications
Tertulien Ndjountche
CRC Press
Taylor & Francis Group
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Version Date: 20180813
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Contents
Preface xi
New to this edition . . . . . . . . . . . . . . . . . . . . . . . . . . xii
Content overview . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv
1 Mixed-Signal Integrated Systems: Limitations and Chal-
lenges 1
1.1 Integrated circuit design flow . . . . . . . . . . . . . . . . . . 2
1.2 Design technique issues . . . . . . . . . . . . . . . . . . . . . 6
1.3 Integrated system perspectives . . . . . . . . . . . . . . . . . 7
1.4 Built-in self-test structures . . . . . . . . . . . . . . . . . . . 8
1.5 Concluding remarks . . . . . . . . . . . . . . . . . . . . . . . 9
1.6 To probe further . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Data Converter Principles 11
2.1 Binary codes . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.1 Unipolar codes . . . . . . . . . . . . . . . . . . . . . . 15
2.1.2 Bipolar codes . . . . . . . . . . . . . . . . . . . . . . . 17
2.1.3 Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2 Data converter characterization . . . . . . . . . . . . . . . . 19
2.2.1 Quantization errors. . . . . . . . . . . . . . . . . . . . 19
2.2.2 Errors related to circuit components . . . . . . . . . . 23
2.2.3 Static errors. . . . . . . . . . . . . . . . . . . . . . . . 26
2.2.4 Dynamic errors . . . . . . . . . . . . . . . . . . . . . . 28
2.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Bibliography 33
3 Nyquist Digital-to-Analog Converters 35
3.1 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . 36
3.1.1 Binary-weightedstructure . . . . . . . . . . . . . . . . 38
3.1.2 Thermometer-coded structure . . . . . . . . . . . . . . 38
3.1.3 Segmented architecture . . . . . . . . . . . . . . . . . 38
3.2 Voltage-scaling DACs . . . . . . . . . . . . . . . . . . . . . . 39
3.2.1 Basic resistor-string DAC . . . . . . . . . . . . . . . . 39
3.2.2 Intermeshed resistor-string DAC . . . . . . . . . . . . 45
3.2.3 Two-stage resistor-stringDAC . . . . . . . . . . . . . 46
v
vi Contents
3.3 Current-scaling DACs . . . . . . . . . . . . . . . . . . . . . . 49
3.3.1 Binary-weightedresistor DAC . . . . . . . . . . . . . . 49
3.3.2 R-2R ladder DAC . . . . . . . . . . . . . . . . . . . . 50
3.3.3 Switched-current DAC . . . . . . . . . . . . . . . . . . 51
3.3.3.1 Static nonlinearity errors . . . . . . . . . . . 58
3.3.3.2 Current source sizing . . . . . . . . . . . . . 62
3.3.3.3 Switching scheme . . . . . . . . . . . . . . . 63
3.3.4 NRZ and RZ SC DAC . . . . . . . . . . . . . . . . . . 67
3.4 Charge-scaling DAC . . . . . . . . . . . . . . . . . . . . . . . 68
3.5 Hybrid DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.6 Configuring a unipolar DAC for the bipolar conversion . . . 75
3.7 Algorithmic DAC . . . . . . . . . . . . . . . . . . . . . . . . 78
3.8 Direct digital synthesizer . . . . . . . . . . . . . . . . . . . . 79
3.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.10 Circuit design assessment . . . . . . . . . . . . . . . . . . . . 82
Bibliography 89
4 Nyquist Analog-to-Digital Converters 91
4.1 Analog-to-digital converter (ADC) architectures . . . . . . . 92
4.1.1 Successive approximationregister ADC . . . . . . . . 92
4.1.2 Integrating ADC . . . . . . . . . . . . . . . . . . . . . 108
4.1.3 Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . 115
4.1.4 Averaging ADC . . . . . . . . . . . . . . . . . . . . . . 127
4.1.5 Folding and interpolating ADC . . . . . . . . . . . . . 131
4.1.6 Sub-ranging ADC . . . . . . . . . . . . . . . . . . . . 142
4.1.7 Pipelined ADC . . . . . . . . . . . . . . . . . . . . . . 143
4.1.8 Algorithmic ADC. . . . . . . . . . . . . . . . . . . . . 155
4.1.9 Time-interleaved ADC . . . . . . . . . . . . . . . . . . 159
4.2 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
4.3 Circuit design assessment . . . . . . . . . . . . . . . . . . . . 164
Bibliography 179
5 Delta-Sigma Data Converters 183
5.1 Delta-sigma analog-to-digitalconverter . . . . . . . . . . . . 184
5.1.1 Time domain behavior . . . . . . . . . . . . . . . . . . 185
5.1.2 Linear model of a discrete-time modulator . . . . . . . 188
5.1.3 Modulator dynamic range . . . . . . . . . . . . . . . . 189
5.1.4 Continuous-time modulator . . . . . . . . . . . . . . . 194
5.1.5 Lowpass delta-sigma modulator . . . . . . . . . . . . . 197
5.1.5.1 Single-stage modulator with a 1-bit quantizer 197
5.1.5.2 Dithering . . . . . . . . . . . . . . . . . . . . 201
5.1.5.3 Design examples . . . . . . . . . . . . . . . . 202
5.1.5.4 Modulator architectures with a multi-bit
quantizer . . . . . . . . . . . . . . . . . . . . 210
Contents vii
5.1.5.5 Cascaded modulator . . . . . . . . . . . . . . 213
5.1.5.6 Effect of the multi-bit DAC nonlinearity. . . 222
5.1.5.7 Quantizationnoise-shapingandinter-stageco-
efficient scaling . . . . . . . . . . . . . . . . . 223
5.1.6 Bandpass delta-sigma modulator . . . . . . . . . . . . 224
5.1.6.1 Single-loop bandpass delta-sigma modulator 225
5.1.6.2 Cascaded bandpass delta-sigma modulator . 226
5.1.6.3 Design examples . . . . . . . . . . . . . . . . 227
5.1.7 DT modulator synthesis . . . . . . . . . . . . . . . . . 234
5.1.8 CT modulator synthesis . . . . . . . . . . . . . . . . . 235
5.1.9 Decimation filter . . . . . . . . . . . . . . . . . . . . . 238
5.2 Delta-sigma digital-to-analogconverter . . . . . . . . . . . . 258
5.2.1 Interpolation filter . . . . . . . . . . . . . . . . . . . . 258
5.2.2 Digital modulator . . . . . . . . . . . . . . . . . . . . 266
5.3 Nyquist DAC design issues . . . . . . . . . . . . . . . . . . . 270
5.3.1 Vector-feedback DEM . . . . . . . . . . . . . . . . . . 270
5.3.2 Data-weighted averaging technique . . . . . . . . . . . 275
5.3.2.1 Element selection logic based on a tree struc-
ture and butterfly shuffler . . . . . . . . . . . 276
5.3.2.2 Generalized DWA structure . . . . . . . . . . 280
5.4 Data converter testing and characterization . . . . . . . . . . 282
5.4.1 Histogram-basedtesting . . . . . . . . . . . . . . . . . 282
5.4.2 Spectral analysis method . . . . . . . . . . . . . . . . 285
5.4.3 Walsh transform-basedtransfer function estimation . 286
5.4.4 Testing using sine-fit algorithms . . . . . . . . . . . . 287
5.5 Delta-sigma modulator-based oscillator . . . . . . . . . . . . 287
5.6 Digital signal processor interfacing with data converters . . . 290
5.6.1 Parallel interfacing . . . . . . . . . . . . . . . . . . . . 293
5.6.2 Serial interfacing . . . . . . . . . . . . . . . . . . . . . 294
5.7 Built-in self-test structures for data converters . . . . . . . . 295
5.8 Circuit design assessment . . . . . . . . . . . . . . . . . . . . 298
Bibliography 319
6 Circuits for Signal Generation and Synchronization 325
6.1 Generation of clock signals with nonoverlapping phases . . . 327
6.2 Phase-locked loop . . . . . . . . . . . . . . . . . . . . . . . . 329
6.2.1 PLL linear model . . . . . . . . . . . . . . . . . . . . . 330
6.2.2 Charge-pump PLL . . . . . . . . . . . . . . . . . . . . 333
6.3 Charge-pump PLL building blocks . . . . . . . . . . . . . . . 334
6.3.1 Phase and frequency detector . . . . . . . . . . . . . . 334
6.3.2 Phase detector . . . . . . . . . . . . . . . . . . . . . . 337
6.3.2.1 Linear phase detector . . . . . . . . . . . . . 338
6.3.2.2 Binary phase detector . . . . . . . . . . . . . 339
6.3.2.3 Half-rate phase detector . . . . . . . . . . . . 340
viii Contents
6.3.3 Charge-pump circuit . . . . . . . . . . . . . . . . . . . 343
6.3.4 Loop filter . . . . . . . . . . . . . . . . . . . . . . . . . 346
6.3.5 Voltage-controlledoscillator . . . . . . . . . . . . . . . 348
6.4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
6.4.1 Frequency synthesizer . . . . . . . . . . . . . . . . . . 355
6.4.2 Clock and data recovery . . . . . . . . . . . . . . . . . 366
6.4.2.1 Dual-loop CDR . . . . . . . . . . . . . . . . 372
6.4.2.2 Phase interpolator-basedCDR circuit . . . . 374
6.4.2.3 CDR circuit based on a gated VCO . . . . . 377
6.4.2.4 Reference-less dual-loop CDR circuit . . . . 381
6.4.2.5 Reference-lesssingle-loopCDR circuitusing a
linear phase detector. . . . . . . . . . . . . . 384
6.5 Delay-locked loop . . . . . . . . . . . . . . . . . . . . . . . . 389
6.6 PLL with a built-in self-test structure . . . . . . . . . . . . . 393
6.6.1 Gain, capture and lock range, and lock time . . . . . . 394
6.6.2 Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
6.7 PLL specifications . . . . . . . . . . . . . . . . . . . . . . . . 402
6.8 VCO-based analog-to-digitalconverter . . . . . . . . . . . . 404
6.9 PLL based on time-to-digital converter . . . . . . . . . . . . 406
6.9.1 Flash TDC . . . . . . . . . . . . . . . . . . . . . . . . 408
6.9.2 Vernier TDC . . . . . . . . . . . . . . . . . . . . . . . 409
6.9.3 Switched ring oscillator TDC . . . . . . . . . . . . . . 410
6.10 High-speed input/output link transceiver . . . . . . . . . . . 413
6.11 Relaxation oscillator . . . . . . . . . . . . . . . . . . . . . . . 425
6.12 Class D amplifier . . . . . . . . . . . . . . . . . . . . . . . . 426
6.13 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
6.14 Circuit design assessment . . . . . . . . . . . . . . . . . . . . 432
Bibliography 447
Appendix A Logic Building Blocks 453
A.1 Boolean algebra . . . . . . . . . . . . . . . . . . . . . . . . . 453
A.1.1 Basic operations . . . . . . . . . . . . . . . . . . . . . 453
A.1.2 Exclusive-OR and equivalence operations . . . . . . . 454
A.2 Combinational logic circuits . . . . . . . . . . . . . . . . . . 454
A.2.1 Basic gates . . . . . . . . . . . . . . . . . . . . . . . . 454
A.2.2 CMOS implementation. . . . . . . . . . . . . . . . . . 457
A.3 Sequential logic circuits . . . . . . . . . . . . . . . . . . . . . 461
A.3.1 Asynchronous SR latch . . . . . . . . . . . . . . . . . 461
A.3.2 Asynchronous SR latch . . . . . . . . . . . . . . . . . 461
A.3.3 D latch . . . . . . . . . . . . . . . . . . . . . . . . . . 462
A.3.4 D flip-flops . . . . . . . . . . . . . . . . . . . . . . . . 462
A.3.5 CMOS implementation. . . . . . . . . . . . . . . . . . 464
A.4 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
Contents ix
Appendix B Notes on Circuit Analysis 471
B.1 Radius of curvature . . . . . . . . . . . . . . . . . . . . . . . 471
B.2 Spectral analysis of PWM signals . . . . . . . . . . . . . . . 474
B.3 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
Index 481