Current Sense Amplifiers: for Embedded SRAM in High-Performance System-on-a-Chip Designs

168 Pages·2003·5.56 MB·English

by  Dr. Bernhard Wicht (auth.)

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12 Current Sense Amplifiers
for Embedded SRAM in High-Performance System-on-a-Chip Designs
ByB. Wicht
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B. Wicht
Current Sense Amplifiers
for Embedded SRAM
in High-Performance
System-on-a-Chip Designs
With 125 Figures
t
Springer
Dr. Bernhard Wicht
Technische Universităt Munchen
Lehrstuhl fiir Technische Elektronik
Arcisstrasse 21
80333 Munchen, Germany
Series Editors:
Dr. Kiyoo Itoh
Hitachi Ltd., Central Research Laboratory, 1-280 Higashi-Koigakubo
Kokubunji-shi, Tokyo 185-8601, Japan
Professor Thomas Lee
Stanford University, Department of Electrica! Engineering, 420 Via Palou Mall, CIS-205
Stanford, CA 94305-4070, USA
Professor Takayasu Sakurai
Center for Collaborative Research, University of Tokyo, 7-22-1 Roppongi
Minato-ku, Tokyo 106-8558, Japan
Professor Willy M. C. Sansen
Katholieke Universiteit Leuven, ESAT-MICAS, Kasteelpark Arenberg 10
3001 Leuven, Belgium
Professor Doris Schmitt-Landsiedel
Technische Universităt Munchen, Lehrstuhl fiir Technische Elektronik
Theresienstrasse 90, Gebăude N3, 80290 Munchen, Germany
ISSN 1437-0387
ISBN 978-3-642-05557-7
Library of Congress Cataloging-in-Publication Data: Wicht, B. (Bernhard), 1970-. Current sense amplifiers:
for embedded SRAM in high-performance system-on-a-chip designs 1 B. Wicht. p. cm. - (Springer series
in advanced microelectronics ; 12) Includes bibliographical references and index.
ISBN 978-3-642-05557-7 ISBN 978-3-662-06442-9 (eBook)
DOI 10.1007/978-3-662-06442-9
1. Direct current amplifiers. 2. Systems onan chip. 3. Ammeters. !. Title. II. Series. TK7871.58.D5W53
2003 621.39'5-dc21 2003042528
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Preface
System-on-a-chip (SoC) designs result in a wide range of high-complexity,
high-value semiconductor products. As the technology scales towards smaller
feature sizes and chips grow larger, a speed limitation arises due to an in
creased RC delay associated with interconnection wires. Innovative circuit
techniques are required to achieve the speed needed for high-performance
signal processing. Current sensing is considered as a promising circuit class
since it is inherently faster than conventional voltage sense amplifiers. How
ever, especially in SRAM, current sensing has rarely been used so far. Practi
cal implementations are challenging because they require sophisticated analog
circuit techniques in a digital environment.
The objective of this book is to provide a systematic and comprehen
sive insight into current sensing techniques. Both theoretical and practical
aspects are covered. Design guidelines are derived by systematic analysis of
different circuit principles. Innovative concepts like compensation of the bit
line multiplexer and auto-power-down will be explained based on theory and
experimental results.
The material will be interesting for design engineers in industry as well as
researchers who want to learn about and apply current sensing techniques.
The focus is on embedded SRAM but the material presented can be adapted
to single-chip SRAM and to any other current-providing memory type as well.
This includes emerging memory technologies like magnetic RAM (MRAM)
and Ovonic Unified Memory (OUM). Moreover, it is also applicable to array
like structures such as CMOS camera chips and to circuits for signal trans
mission along highly capacitive busses.
The fundamental SRAM structure and sensing schemes are presented in
Chap. 2. General properties of voltage and current sensing are discussed. The
performance in terms of speed including a transmission line model of the bit
line is investigated. Even though the general emphasis is on current sensing,
in Chap. 3 voltage sense amplifiers are considered since they will remain
as a comparator block in current sense amplifiers. As a main consideration,
Chap. 4 presents circuit principles for current sensing. A classification distin
guishes four different types of current sensing, each in a single-ended version
and in a fully-differential implementation introduced in this book. All types
are characterized and compared in terms of power, delay and area, but also
VI Preface
with respect to stability, robustness and operation at low supply voltages.
The comparison also incorporates voltage sensing and gives future trends.
A main limitation of the practical use of current sense amplifiers has been
the finite resistance of the bitline multiplexer. Chapter 5 analyzes its influ
ence and presents a method to overcome this effect by means of a current
sense amplifier with improved feedback structure. The proposed solution is
the first current sense amplifier which fully compensates for the influence of
the bitline multiplexer in terms of delay and signal amplitude. The memory
cell, in particular the cell stability, is considered in Chap. 6. This applies
to voltage as well as current sensing. An analytical model is derived which
determines a minimum bitline dc potential that guarantees stable read oper
ation. The theory is confirmed by measurements and used to derive a trend
for future technologies. Chapter 7 covers implementation aspects of current
sense amplifiers and gives a design example. Circuits for power-down and
precharge are presented. Measurements prove that the design example oper
ates at a supply voltage as low as 0.7V. The appendix provides additional
theoretical investigations and experimental data. A brief summary at the end
of each chapter provides a quick reference for those readers who want to get
an overview without going through all the details.
This book is based on my research at the Institute for Technical Electron
ics of the Technische Universitiit Munchen in cooperation with the Memory
Compiler Development Group of Infineon Technologies. I am deeply grateful
to Prof. Doris Schmitt-Landsiedel and to Dr. Steffen Paul (Infineon) for their
advice and support in a creative and friendly atmosphere. I am indebted
to many colleagues at Infineon Technologies, especially Andrea Jans, Yan
nick Martelloni, Thomas Nirschl, Anthony Sanders, Dr. Ulf Schlichtmann,
Dirk Schulz, and Gary Waugh. Special thanks to Jean-Yves Larguier for the
excellent team work and to Bernd Kruger and Rupert Thanner for their out
standing support during the measurements. I want to thank the Institute
for Electronic Design Automation of the Technische Universitiit Munchen for
providing the design tool WiCkeD.
Munich, January 2003 Bernhard Wicht
Contents
1. Introduction.... ........ ...... .. .......................... 1
2. Fundamentals of SRAM and Sensing. ...... .......... .... 5
2.1 Static Random Access Memory (SRAM) .................. 5
2.2 Methods of Sensing: Voltage Sensing - Current Sensing. . . . . . 8
2.3 Sensing Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10
2.4 Summary.. ..... ...... ........ ..... ...... .... ...... .... 13
3. Voltage Sense Amplifiers ................................. 15
3.1 Principles and Typical Circuits. . . . . . . . . . . . . . . . . . . . . . . . . .. 15
3.1.1 Static Voltage Sense Amplifiers (Static Comparators). 15
3.1.2 Dynamic Voltage Sense Amplifiers
(Latch-Type Sense Amplifiers) . . . . . . . . . . . . . . . . . . . .. 16
3.2 A Latch-Type Sense Amplifier for Current Sensed SRAM. . .. 20
3.2.1 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20
3.2.2 Delay.. .. ........ ....... ................... ..... 22
3.2.3 yield. ... ........ ............... ... ..... ... ..... 25
3.2.4 Yield Improvement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 28
3.2.5 Optimum Input DC level VI N DC . . . . . . . . . . . . . . . . . .. 31
3.2.6 Transistor Sizing, Temperature. . . . . . . . . . . . . . . . . . . .. 34
3.2.7 Comparison to Conventional Latch . . . . . . . . . . . . . . . .. 35
3.2.8 Design Guideline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 36
3.3 Summary........... ....... ....... .............. .. ... .. 36
4. Circuit Principles for Current Sensing . . . . . . . . . . . . . . . . . . .. 39
4.1 Introduction.. ................. .... ...... ......... ..... 39
4.2 Type A - Cascode and Diode Connection. . . . . . . . . . . . . . . . .. 41
4.3 Type B - Regulated Cascode . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 44
4.3.1 Single-Ended Current Sensing. . . . . . . . . . . . . . . . . . . . .. 44
4.3.2 Differential Current Sensing .... ....... ...... ...... 48
4.3.3 Delay......... ..... ..... ..... .... .. ........... .. 49
4.4 Type C - Negative Impedance Converter ......... ......... 54
4.4.1 Single-Ended Current Sensing. . . . . . . . . . . . . . . . . . . . .. 54
4.4.2 Differential Current Sensing ... ............ ....... . 58
VIII Contents
4.4.3 Delay ........................................... 60
4.4.4 Implementation Examples . . . . . . . . . . . . . . . . . . . . . . . .. 62
4.5 Type D - Wilson Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 64
4.5.1 Single-Ended Current Sensing. . . . . . . . . . . . . . . . . . . . .. 64
4.5.2 Differential Current Sensing ... .. .................. 67
4.5.3 Delay..................... ...................... 69
4.6 Offset Comparison Between Type Band D ........ .. ...... 71
4.7 Conclusion.. ................................. ... .... .. 75
4.7.1 Delay Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 75
4.7.2 Future Technologies ............................ .. 76
4.7.3 Small-Signal Versus Large-Signal Analysis. . . . . . . . . .. 76
4.7.4 Overall Comparison .............................. 77
4.8 Summary..... .............. .......... .... ....... .... .. 78
5. Analysis and Compensation of the Bitline Multiplexer. . .. 81
5.1 Introduction........................................... 81
5.2 Analysis of the Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 82
5.2.1 General Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . .. 82
5.2.2 Analysis for Ts = 0 .... ...................... ..... 83
5.2.3 Analysis for Ts i- 0 ............................... 84
5.3 Principle of Multiplexer Compensation. . . . . . . . . . . . . . . . . . .. 88
5.4 Type D ........ ....... .. .......... .. ........... ... .... 88
5.4.1 Behavior with Multiplexer. . . . . . . . . . . . . . . . . . . . . . . .. 88
5.4.2 Multiplexer Compensation. . . . . . . . . . . . . . . . . . . . . . . .. 90
5.4.3 Step Response .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 93
5.5 Type B ............... ..................... .. ......... 94
5.6 Type A and C ... .............. ........................ 95
5.7 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 97
5.8 Summary..................... ......................... 99
6. Interaction with the Memory Cell ......... ............... 101
6.1 Stability .. ......................... ..... ............... 101
6.1.1 Mechanism of Cell Instability .. ... ................. 101
6.1.2 Critical Bitline Voltage ...................... ... ... 104
6.1.3 Technology Trend ........................ ........ 106
6.2 Cell Current ........................................... 107
6.3 Summary ..... .. ..... ..... ...... .................. .. ... 108
7. Implementation Aspects .................................. 109
7.1 Design Procedure ..................... ... ....... .. ...... 110
7.2 Circuit Characterization ................. ................ 113
7.3 Power-Down and Precharge ........................ .. .... 116
7.4 System Performance .. .... ... ................. ......... . 121
7.5 Summary ............. .... .. ................. .......... 125
Contents IX
8. Outlook 127
A. Two-Pole Transfer Function ..... .... ............ ... ... .. . 129
B. Step Response ... ............ .............. .... ........... 131
C. Common-Mode Stability .................................. 135
D. Delay Versus Supply Voltage .... .......... ............... 141
E. Experimental Results: Current Sensing ... .. .............. 145
F. Experimental Results: Voltage Sensing ................... 149
Bibliography ........ ......... .. ...... .. ....... .. ...... .. .. ... . 150
Index .......... .............. ... .. ...... ..... .. ........... ... . 159
List of Symbols
small-signal voltage gain
dc voltage gain, Ao = A(s = 0)
common-mode voltage gain
differential voltage gain (differential input / output)
absolute value of CMOS inverter voltage gain
general polynomial coeffcient
number of bits of the SRAM input/output word;
polynomial coeffcient
logic value of internal storage node of the 6-T memory cell
load capacitance
total bit line capacitance
value at transition between the delay equations for small and
large GBL
bitline capacitance at delay crossover between voltage and
current sensing
G~3L bitline capacitance per unit length
G~Ln bitline capacitance per memory cell
G load capacitance
L
CMRR common-mode rejection ratio
G~x gate-channel (oxide) capacitance per unit area
general constants
Cl, C2, C3, C4
D damping coefficient
DB damping coefficient of Type B current sensing
DD damping coefficient of Type D current sensing
de,dv factors in the delay expression for £urrent and yoltage sensing
errl,err2 relative error of different approximations of rms
ECL relative GL-mismatch at voltage sense amplifier outputs,
ECL· G = a(Gd
L
frequency
figure of merit
factors describing the increase of rms for rs i= 0
current transfer function
common-mode current transfer function
dc value of the current transfer function G (current gain)