Crosstalk in Modern On-Chip Interconnects: A FDTD Approach

126 Pages·2016·4.636 MB·English

by  B.K. Kaushik, V. Ramesh Kumar, Amalendu Patnaik (auth.)

SPRINGER BRIEFS IN
APPLIED SCIENCES AND TECHNOLOGY
Brajesh Kumar Kaushik
V. Ramesh Kumar
Amalendu Patnaik
Crosstalk in
Modern On-Chip
Interconnects
A FDTD Approach
123
SpringerBriefs in Applied Sciences
and Technology
More information about this series at http://www.springer.com/series/8884
Brajesh Kumar Kaushik V. Ramesh Kumar
(cid:129)
Amalendu Patnaik
Crosstalk in Modern
On-Chip Interconnects
A FDTD Approach
123
BrajeshKumar Kaushik Amalendu Patnaik
Department ofElectronics and Department ofElectronics and
Communication Engineering Communication Engineering
Indian Institute of Technology Roorkee Indian Institute of Technology Roorkee
Roorkee,Uttarakhand Roorkee,Uttarakhand
India India
V.RameshKumar
Department ofElectronics and
Communication Engineering
Indian Institute of Technology Roorkee
Roorkee,Uttarakhand
India
ISSN 2191-530X ISSN 2191-5318 (electronic)
SpringerBriefs inApplied SciencesandTechnology
ISBN978-981-10-0799-6 ISBN978-981-10-0800-9 (eBook)
DOI 10.1007/978-981-10-0800-9
LibraryofCongressControlNumber:2016934012
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Preface
Advancement in VLSI technology offers gigascale integrated circuits in a system
on-chip. In such circuits, interconnects play a key role in determining circuit per-
formance such as time delay and power consumption. At high operating frequen-
cies, the closely packed interconnects produce transient crosstalk. The crosstalk
noise strongly influences the signal propagation delay and also causes logic or
functionalfailure.Therefore,itisdesirabletoaccuratelymodelthecrosstalkeffects
in the on-chip interconnects.
Overtheyears,severalmathematicalmodelshavebeenproposedfortheanalysis
ofCMOS-gate-drivencoupledinterconnectlines.However,mostofthesecrosstalk
noise models consider the nonlinear CMOS driver as a linear resistor. This
approximation is not valid for on-chip interconnects because during the input and
output transition states the MOSFET operates in cutoff, linear, and saturation
regions.TheMOSFEToperatingtimeinthesaturationregionisabout50%during
thetransitionperiod.Moreover,theequivalentresistancevalueinsaturationregion
ismuchhigherthanthelinearregion.Thus,assumingthatthetransistoroperatesin
thelinearregionduringthetransitionstateleadstosevereerrorsintheperformance
estimation of the driver interconnect load system. Therefore, it is necessary to
develop an accurate model that appropriately considers the nonlinear effects of
CMOS driver and accurately measures the crosstalk-induced performance param-
eters of on-chip interconnects. This book presents an accurate and time efficient
model of CMOS-gate-driven coupled interconnects for crosstalk-induced perfor-
mance analysis by considering the nonlinear effects of CMOS driver.
The conventional interconnect copper material suffers due to lower reliability
withdownscalingofinterconnectdimensions.ThereliabilityofCudecreasesdueto
electromigration-inducedproblemssuchashillockandvoidformations.Moreover,
with highly scaled dimensions the resistivity of copper increases due to
electron-surfacescatteringandgrain-boundaryscattering.Therefore,researchersare
forced to find an alternative material for on-chip interconnects. Carbon nanotubes
(CNTs)havebeenproposedasapromisinginterconnectmaterial.Aportionofthis
bookisfocusedtowardmodelingofMWCNTinterconnects.Basedontheelectrical
v
vi Preface
equivalent model, an accurate FDTD model is presented while incorporating the
quantum effects of nanowire and nonlinear effects of CMOS driver. The crosstalk
noise is comprehensively analyzed by examining both functional and dynamic
crosstalk effects.
Graphene nanoribbon (GNR), astrip ofultrathinwidth graphene layer,hasalso
been considered aggressively by researchers as a potential alternative material for
realizing on-chip interconnects. Most of the physical and electrical properties of
GNRs are similar to that of CNTs; however, the major advantage of GNRs over
CNTs is that both transistor and interconnect can be fabricated on the same con-
tinuous graphene layer, thus avoiding the metal-graphene contact problems. This
book presents an accurate model for the analysis of MLGNR interconnects using
the FDTD technique. In a more realistic manner, the model incorporates the
width-dependent MFP parameter that helps in accurately estimating the
crosstalk-inducedperformanceincomparisontoconventionalmodels.Moreover,a
comparative analysis of crosstalk-induced performance is presented among Cu,
MWCNT, and MLGNR interconnects.
The stability of the FDTD technique is constrained by the
Courant-Friedrichs-Lewy (CFL) stability condition. Hence, beyond the CFL con-
dition, the technique is unstable and within it, the technique is inefficient. The
efficiencyimprovementsintheFDTDtechniquecanbeeasilyaddressediftheCFL
stability condition is removed by implicitly deriving the transmission line equa-
tions. To improve the efficiency of the FDTD technique, an unconditionally stable
FDTD (US-FDTD) technique is presented for the analysis of MLGNR
interconnects.
ThisbookprovidesanaccurateFDTDmodelforon-chipinterconnects,covering
most recent advancements in materials and design. Furthermore, depending on the
geometry and physical configurations, different electrical equivalent models for
CNT and GNR-based interconnects are presented. Based on the electrical equiva-
lent models the performance comparison among the Cu, CNT, and GNR-based
interconnects are also discussed. The proposed models are validated with the
HSPICE simulations. The organization of the book is as follows: Chap. 1 intro-
ducesthecurrentresearchscenarioinmodelingofon-chipinterconnects.Chapter2
presents the structure, properties, and characteristics of graphene based on-chip
interconnects.TheFDTDmodelingofCu-basedon-chipinterconnectsispresented
inChap.3.ThemodelconsidersthenonlineareffectsofCMOSdriveraswellasthe
transmissionlineeffectsofinterconnectlinethatincludescouplingcapacitanceand
mutual inductance effects. Chapter 4 introduces an equivalent single conductor
(ESC) model of MWCNT interconnects. Based on the ESC model, this chapter
presents an accurate FDTD model of MWCNT while incorporating the quantum
effects of nanowire and nonlinear effects of CMOS driver. The modeling of
MLGNR interconnects using the FDTD technique is presented in Chap. 5. In a
more realistic manner, the proposed model includes the effect of width-dependent
MFP of the MLGNR while taking into account the edge roughness. Finally, to
Preface vii
improve the efficiency of the FDTD model, an unconditionally stable FDTD
technique is presented for the analysis of on-chip interconnects in Chap. 6.
Moreover, the performance of Cu interconnect is compared with MWCNT and
MLGNR interconnects under the influence of crosstalk.
Contents
1 Introduction to On-Chip Interconnects and Modeling . . . . . . . . . . . 1
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Evolution of Interconnect Materials . . . . . . . . . . . . . . . . . . . . . . 2
1.2.1 Carbon Nanotubes (CNTs). . . . . . . . . . . . . . . . . . . . . . . 3
1.2.2 Graphene Nanoribbons (GNRs). . . . . . . . . . . . . . . . . . . . 4
1.3 Modeling of On-Chip Interconnects. . . . . . . . . . . . . . . . . . . . . . 4
1.4 Introduction to FDTD Method. . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4.1 Central Difference Approximation. . . . . . . . . . . . . . . . . . 7
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Interconnect Modeling, CNT and GNR Structures, Properties,
and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Interconnect Modeling Approaches . . . . . . . . . . . . . . . . . . . . . . 11
2.1.1 Lumped Model with CMOS Driver. . . . . . . . . . . . . . . . . 11
2.1.2 Distributed Model with Resistive Driver. . . . . . . . . . . . . . 12
2.1.3 Distributed Model with CMOS Driver. . . . . . . . . . . . . . . 13
2.2 Carbon Nanotubes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.1 Basic Structure of CNTs . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.2 Semiconducting and Metallic CNTs. . . . . . . . . . . . . . . . . 18
2.2.3 Properties and Characteristics of CNTs . . . . . . . . . . . . . . 20
2.2.4 Conductivity Comparison. . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.5 MWCNT Interconnect Modeling. . . . . . . . . . . . . . . . . . . 24
2.2.6 MWCNT Performance Analysis . . . . . . . . . . . . . . . . . . . 28
2.3 Graphene Nanoribbons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.1 Basic Structure of GNRs . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.2 Semiconducting and Metallic GNRs . . . . . . . . . . . . . . . . 31
2.3.3 Properties and Characteristics of GNRs . . . . . . . . . . . . . . 31
2.3.4 Conductivity Comparison. . . . . . . . . . . . . . . . . . . . . . . . 33
2.3.5 MLGNR Interconnect Modeling . . . . . . . . . . . . . . . . . . . 34
2.3.6 MLGNR Performance Analysis. . . . . . . . . . . . . . . . . . . . 36
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
ix
x Contents
3 FDTD Model for Crosstalk Analysis of CMOS Gate-Driven
Coupled Copper Interconnects. . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3 FDTD Model of CMOS Gate-Driven Cu Interconnects. . . . . . . . . 47
3.3.1 FDTD Model of Coupled Interconnects . . . . . . . . . . . . . . 48
3.3.2 Incorporation of Boundary Constraints. . . . . . . . . . . . . . . 50
3.4 Validation of the Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.5 Extended Three Coupled Interconnect Lines . . . . . . . . . . . . . . . . 56
3.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4 FDTD Model for Crosstalk Analysis of Multiwall Carbon
Nanotube (MWCNT) Interconnects . . . . . . . . . . . . . . . . . . . . . . . . 61
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.2 Equivalent Single Conductor Model of the MWCNT
Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.2.1 Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.2.2 Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.2.3 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.3 FDTD Model of MWCNT Interconnect . . . . . . . . . . . . . . . . . . . 68
4.3.1 The MWCNT Interconnect Line . . . . . . . . . . . . . . . . . . . 68
4.3.2 Boundary Condition at Near-End Terminal. . . . . . . . . . . . 70
4.3.3 Boundary Condition at Far-End Terminal. . . . . . . . . . . . . 71
4.4 Validation of the Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.5 Sensitivity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.5.1 Sensitivity Analysis for Number of Conducting
Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.5.2 Sensitivity Analysis for Contact Resistance. . . . . . . . . . . . 76
4.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5 Crosstalk Modeling with Width Dependent MFP in MLGNR
Interconnects Using FDTD Technique. . . . . . . . . . . . . . . . . . . . . . . 81
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.2 Equivalent Single Conductor Model of the MLGNR
Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.2.1 Transient Analysis of MTL and ESC Models . . . . . . . . . . 85
5.3 FDTD Model of the MLGNR Interconnect. . . . . . . . . . . . . . . . . 86