Table Of ContentComputer Design Aids for VLSI Circuits
NATO ASI Series
Advanced Science Institutes Series
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Series E: Applied Sciences - No. 48
Computer Design Aids
for VLSI Circuits
edited by
P. Antognetti
Istituto di Elettrotecnica
University of Genova
Italy
D.O. Pederson
EECS Department
University of California
Berkeley, California, USA
H. de Man
Laboratory ESAT
Catholic University of Leuven
Heverlee, Belgium
1986 Martinus Nijhoff Publishers
Dordrecht I Boston I Lancaster
Published in cooperation with NATO Scientific Affairs Division
Proceedings of the NATO Advanced Study Institute on Computer Design Aids for
VLSI Circuits, Urbino, Italy, July 21-August 1, 1980
ISBN-13: 978-94-011-8008-5 e-ISBN-13: 978-94-011-8006-1
001: 10.1007/978-94-011-8006-1
Distributors for the United States and Canada: Kluwer Boston, Inc., 190 Old Derby
Street, Hingham, MA 02043, USA
Distributors for all other countries: Kluwer Academic Publishers Group, Distribution
Center, P.O. Box 322,3300 AH Dordrecht, The Netherlands
Fi rst edition 1981
Second printing 1984
Third printing 1986
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Copyright © 1984 by Martinus Nijhoff Publishers, Dordrecht
Softcover reprint of the hardcover 1s t edition 1984
v
FOREWORD
The Nato Advanced Study Institute on "Computer Design Aids for
VLSI Circuits" was held from July 21 to August 1, 1980 at
Sogesta, Urbino, Italy. Sixty-three carefully chosen profes
sionals were invited to participate in this institute together
with 12 lecturers and 7 assistants. The 63 participants were
selected from a group of almost 140 applicants. Each had the
background to learn effectively the set of computer IC design
aids which were presented. Each also had individual expertise in
at least one of the topics of the Institute.
The Institute was designed to provide hands-on type of experience
rather than consisting of solely lecture and discussion. Each
morning, detailed presentations were made concerning the critical
algorithms that are used in the various types of computer IC
design aids. Each afternoon a lengthy period was used to provide
the participants with direct access to the computer programs. In
addition to using the programs, the individual could, if his
expertise was sufficient, make modifications of and extensions
to the programs, or establish limitations of these present aids.
The interest in this hands-on activity was very high and many
participants worked with the programs every free hour.
The editors would like to thank the Direction of SOGESTA for the
excellent facilities, R. Riccioni of the SOGESTA Computer
~1r.
Center and Mr. 11. Vanzi of the University of Genova for enabling
all the programs to run smoothly on the set date.
P.Antognetti
D.O.Pederson Urbino, Summer 1980.
H. De man
VII
TABLE OF CONTENTS
Donald O. Pederson
Computer Aids in Integrated Circuits Design
A.L. Sangiovanni-Vincentelli
Circuit Simulation 19
H. De Man, G. Arnout, P. Reynaert
r1ixed-mode Circuit Simulation Techniques and Their
Implementation in DIANA 113
A.R. Newton
Timing, Logic and ~1ixed-mode Simulation for Large MOS
Integrated Circuits 175
H. De Man, J. Vandewalle, J. Rabaey
Simulation of Analog Sampled-data MOSLSI Circuits 241
H.J. Knobloch
Description and Simulation of Complex Digital Systems
by Means of the Register Transfer Language RTS Ia 285
J. Hermet
Functional Simulation 321
T. W. Williams
Design for Testability 359
VIII
Peter S. Bottorff
Computer Aids to Testing - An Overview 417
W. Sansen, W. Heyns, H. Beke
Layout Automation Based on Placement and Routing
Algorithms 465
H.Y. Hsueh
Symbolic Layout Compaction 499
COMPUTER AIDS IN INTEGRATED CIRCUITS DESIGN
Donald O. Pederson
Department of Electrical Engineering and Computer
Sciences and the Electronics Research Laboratory
University of California, Berkeley, California 94720
Today's VLSI and LSI Circuits
A very large-scale integrated (VLSI) circuit is commonly de
fined as a single chip which contains more than 100,000 devices.
This year (1980) several industrial electronic firms are design
ing IC's with device counts of more than 100,000. These circuits
are either in initial design or are possibly in initial prototype
production. Generally, the NMOS technoloqy is being used with a
minimum feature size in the 1-2 micron range. The design method
ology and the computer aids used in the VLSI design, in general,
are those that are also being used in today's LSI production or
are relatively modest extensions of these methodologies and
computer aids for design.
As is typical when a design is attempted with new size
restrictions and with extensions of processing technology, the
design proceeds slowly because there is a great interaction be
tween the design and layout of the circuit functions and the
development of the fabrication technoloqy. Usually the design
team, which will be quite large for VLSI, involves digital and
siqnal processing systems specialists, circuit designers, layout
specialists, testing experts, desion aids quru's, and of course
the processing experts. For new types of it is
circui~s
common that a mixed desiqn strateqy will be used, i.e., a mixture
of different design methodologies will be used. A particular
problem in the development of computer desiqn aids concerns the
fact that with these new developments or the new extensions in
the fabrication and processing technolonv there is little adequ
ate modeling information on the process or the electronic devices.
2
Today's production LSI circuits can be represented by the
80B6 and the 68000 microcomputer circuits initially developed by
Inte 1 and t40toro 1a , respectively. The devi ce count of the former
is approximately 30,000; for the latter, it is about 34,000 (67,000
sites). The development of these circuits commenced in late 1976;
thus, the technology used and the critical feature dimensions were
those of late 1976, but probably modified before the design freeze
to 1977 technology. The total development time for these circuits
was of the order of 32 to 36 months. The design teams numbered
between 20 and 40 and reacheda peak during the layout phase. The
initial layout, before subsequent corrections, took of the order
from 60 to 100 man-months of effort. The development cost was of
the order of 10 to 20 million dollars.
As is typical, even though the technology for these LSI's
was reasonably well established, there was a lag in the develop
ment of the necessary modeling information for the computer
design aids. None-the-less, circuit and logic simulation were
used effectively, the former to develop and evaluate circuits of
the order of 100 transistors, which involved basic building blocks
used in the design. Logic simulation was used on several of the
building blocks of the chips as well as larger portions in order
to verify the logical design as well as to develop through fault
simulation adequate test patterns for the Ie testers. The layout
was mostly accompanied by hand either initially on paper or
directly into a graphical terminal; i.e., automatic desiqn or
synthesis procedures were not used extensively. In the base of
development on mylar, there was a subsequent digitization. For
both, interactive computer correction was used. Design-rule
checkers were used extensively to establish that layout design
rules were verified. Finally, in both cases a breadboard of the
circuit or system was made or attempted. For the 68,000, the
breadboard consisted of MSI and LSI CMOS parts.
The following data illustrate the increase of design, layout,
verification and digitizing time. The early Z-BO microprocessor
contained approximately 8,000 devices and took approximately BO
man weeks of effort for the design, layout, etc. The recently
developed Z8000 microcomputer contains approximately 25,000
devices and took approximately 165-man weeks of effort to design.
The B086, mentioned above, has 30,000 devices and had a corres
ponding design time of 600 man-weeks. The total desiqn and fab
rication time from initial concept to manufactured product was
approximately 350-man weeks for the Z-BOOO microcomputer, approx
imately twice the design time.
Description:The Nato Advanced Study Institute on "Computer Design Aids for VLSI Circuits" was held from July 21 to August 1, 1980 at Sogesta, Urbino, Italy. Sixty-three carefully chosen profes sionals were invited to participate in this institute together with 12 lecturers and 7 assistants. The 63 participant
