Computer Architecture: ISCA 2010 International Workshops A4MMC, AMAS-BT, EAMA, WEED, WIOSCA, Saint-Malo, France, June 19-23, 2010, Revised Selected Papers

400 Pages·2012·7.61 MB·English

by  Michael Lange

Lecture Notes in Computer Science 6161
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Ana Lucia Varbanescu Anca Molnos
Rob van Nieuwpoort (Eds.)
Computer
Architecture
ISCA 2010 International Workshops
A4MMC,AMAS-BT, EAMA, WEED, WIOSCA
Saint-Malo, France, June 19-23, 2010
Revised Selected Papers
1 3
VolumeEditors
AnaLuciaVarbanescu
AncaMolnos
DelftUniversityofTechnology,SoftwareTechnologiesDepartment
2628CDDelft,TheNetherlands
E-mail:{a.l.varbanescu;a.m.molnos}@tudelft.nl
RobvanNieuwpoort
VrijeUnversiteitAmsterdam,DepartmentofComputerScience
1081HVAmsterdam,TheNetherlands
E-mail:[email protected]
ISSN0302-9743 e-ISSN1611-3349
ISBN978-3-642-24321-9 e-ISBN978-3-642-24322-6
DOI10.1007/978-3-642-24322-6
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Preface
The ACM IEEE International Symposium on Computer Architecture (ISCA)
is the premier forum for new ideas and experimental results in computer archi-
tecture. In 2010, the 37th edition of ISCA was held in Saint Malo, France. The
conference received 245 submissions, and accepted 44 of them (an acceptance
rate of 18%).
ISCAhasalongtraditionofhavingstrongworkshopsandtutorialsassociated
with the conference. Thanks to Yanos Sazeides, the Workshop/Tutorial Chair
in2010,severalhigh-qualityworkshopsandtutorialswereagaincollocatedwith
the conference. They were very much appreciated by the attendees, and they
had an important contribution to the overallsuccess of ISCA 2010.
In2010,ISCAfeatured4half-daytutorials,aswellas13workshopsontopics
ranging from novel memory architectures to emerging application design and
performance analysis. This proceedings volume gathers the valuable scientific
contributions from five of these workshops:
1. A4MMC—TheFirstWorkshoponApplications forMulti- andMany-Core
Processors:Analysis,Implementation,andPerformance—focusesentirelyon
application case studies. With A4MMC, the organizers provided a forum
wheremulti-andmanycoreapplicationdesignerscouldexchangeknowledge,
insights and discoveries,and discuss their latest researchadvances.Further,
by collocatingA4MMC with ISCA, the application designand development
community was able to directly expose its findings, requirements,and prob-
lemstoaselectaudienceoftopcomputerarchitectureresearchers.Thiswork-
shop offered an ideal opportunity for software and hardware researchers to
communicateanddebateonhowtofindtherightbalancebetweenthesetwo
sides of the“multicore revolution.”
2. AMAS-BT—The Third Workshop on Architectural and Micro-Archi-
tecturalSupportforBinaryTranslation—ismotivatedbythelarge-scaleuse
of binary translation and on-the-fly code generation, which are becoming
pervasiveas enablersforvirtualization,processormigrationandalsoaspro-
cessor implementation technology. AMAS-BT brought together researchers
and practitioners with the aim of stimulating the exchange of ideas and ex-
periencesonthe potentialandlimits ofarchitecturalandmicroarchitectural
support for binary translation(hence the acronymAMAS-BT). The key fo-
cus is on challenges and opportunities for such assistance and opening new
avenues of research.A secondary goal is to enable dissemination of hitherto
unpublished techniques from commercial projects.
3. EAMA—The Third Workshop on Emerging Applications and Many-core
Architecture—is equally motivated by the emerging workloads that bring
new challengesfor developingfuture computer architectures,andthe break-
throughsincomputersystemdesign,whichenablenewapplicationdomains.
VI Preface
As recent development trends suggest that industry is moving to many-
core architectures to better manage trade-offs among performance, energy
efficiency, and reliability in deep-submicron technology nodes, many oppor-
tunities for developing new classes of applications have opened. Such com-
putationally intensive tasks include real-time ray-tracing,multi-modal data
mining, physical simulation, financial analytics, or virtual worlds. EAMA
broughttogetherapplicationdomainexpertsandcomputerarchitectstodis-
cuss emerging applicationsin these novelfields,as well as their implications
on current- and next-generationmany-core architectures.
4. WEED—TheSecondWorkshoponEnergy-EfficientDesign—providedafo-
rumfortheexchangeofideasonresearchoncriticalareasrelatingtoenergy-
efficient computing, including energy-aware design techniques for systems
(large and small), energy management policies and mechanisms, and stan-
dards for evaluating energy efficiency. It was well attended with a good mix
of researchers and practitioners from industry and academia.
5. WIOSCA—The 6th Annual Workshop on the Interaction Between Oper-
ating System and Computer Architecture—focused on characterizing,mod-
eling and optimizing the interaction between OS and hardware in the light
of emerging architecture paradigms (e.g., multi-core processors), workloads
(e.g., commercial and server workloads) and computing technology (e.g.,
virtualization). The WIOSCA workshop provided an active forum for re-
searchers and engineers from academia and industry to discuss their latest
researchin computer architecture and system software.
February 2011 Ana Lucia Varbanescu
ISCA Workshops Committees
A4MMC: First Workshop on Applications for Multi- and
Many-Cores
Workshop Chairs and Organizers
Henri Bal VrijeUniversiteitAmsterdam,TheNetherlands
Henk Sips Delft University of Technology,
The Netherlands
Ana Lucia Varbanescu Delft University of Technology,
The Netherlands
Anca Molnos Delft University of Technology,
The Netherlands
Rob van Nieuwpoort VrijeUniversiteitAmsterdam,TheNetherlands
Program Committee
John Romein ASTRON, The Netherlands
Sorin Cotofana Delft University of Technology,
The Netherlands
Joerg Keller FernUniversit¨at Hagen, Germany
Christoph Kessler Link¨oping University, Sweden
Rosa Badia Barcelona Supercomputing Center, Spain
Xavier Martorell Universitat Politecnica de Catalunya,Spain
Paul Kelly Imperial College London, UK
Anton Lokhmotov ARM, UK
Raymond Namyst University of Bordeaux, France
David Bader GeorgiaTech,USA
Michael Perrone IBM T.J. Watson Research Center, USA
Virat Agarwal IBM T.J. Watson Research Center, USA
AMAS-BT: Third Workshop on Architectural and
Micro-Architectural Support for Binary Translation
Workshop Chairs and Organizers
Mauricio Breternitz AMD
Robert Cohn Intel
Erik Altman IBM
Youfeng Wu Intel
VIII ISCA WorkshopsCommittees
Program Committee
Erik Altman IBM
Guido Araujo UNICAMP
Edson Borin UNICAMP
Mauricio Breternitz AMD
Mark Charney Intel
Josep M. Codina Intel
Robert Cohn Intel
Andy Glew Intel
Kim Hazelwood University of Virginia
David Kaeli Northeastern University
Chris J. Newburn Intel
Suresh Srinivas Intel
Chenggang Wu CAS, China
Youfeng Wu Intel
EAMA: Third Workshop for Emerging Applications and
Many-Core Architectures
Workshop Chairs and Organizers
Andrea Di Blas Oracle and UC Santa Cruz
Engin Ipek University of Rochester
Victor Lee Intel Corporation
Philipp Slusallek Intel and SaarlandUniversity
Program Committee
Olivier Temam INRIA
David August Princeton University
David Holmes Mayo Clinic
Ravi Murthy Oracle
Milos Prvulovic Georgia Institute of Technology
Jose Renau UC Santa Cruz
Eric Sedlar Oracle
WEED: Second Workshop on Energy-Efficient Design
Workshop Chairs and Organizers
John Carter IBM
Karthick Rajamani IBM
ISCA WorkshopsCommittees IX
Program Committee
Pradip Bose IBM
David Brooks Harvard
Kirk Cameron Virginia Tech
John Carter IBM
Jichuan Chang Hewlett-Packard
Babak Falsafi EPFL
Sudhanva Gurumurthi University of Virginia
Fernando Latorre Intel - UPC
Jie Liu Microsoft
Onur Mutlu Carnegie-MellonUniversity
Karthick Rajamani IBM
Karsten Schwan Georgia Tech
Farhana Sheikh Intel
Thomas Wenisch University of Michigan
WIOSCA
Workshop Chairs and Organizers
Tao Li University of Florida
Onur Mutlu Carnegie Mellon University
James Poe Miami Dade College
Program Committee
Brad Beckmann AMD
Evelyn Duesterwald IBM Research
Alexandra Fedorova Simon Fraser University
Nikos Hardavellas Northwestern University
Jim Larus Microsoft Research
Shan Lu University of Wisconsin
Chuck Moore AMD
Nacho Navarro UPC
Lu Peng Louisiana State University
Partha Ranganathan Hewlett PackardLabs
Ben Sander AMD
Yanos Sazeides University of Cyprus
Per Stenstrom Chalmers University
Osman Unsal Barcelona Supercomputing Center
Kushagra Vaid Microsoft
Wei Wu Intel
Zhao Zhang Iowa State University
A4MMC Foreword
Multi- and manycore processors are here to stay. And this is no longer an aca-
demicrumor,butarealityendorsedandenforcedbyallprocessorvendors.How-
ever,both academia and industry agreethat although the novelprocessorsmay
drill through the power and performance walls, they also open up a new and
wide programmability gap. As technology advances, the software seems to lag
behind more and more. In fact, the multicore world is witnessing a technology
push from the hardware side.
We believe that developing novel hardware, and also software stacks, tools
and programming models is going nowhere if the requirements of the applica-
tions are not takeninto account,or if these platforms are simply too difficult to
program (efficiently). It is, after all, a matter of economics: if we do not focus
on productivity and efficiency, the software development cost per“performance
unit”might become so high that the next generations of multi- and manycores
will simply be unsuccessful.
The best way to initiate productivity and efficiency analyses is to collect a
large enough pool of representative,variate,real-life applications that make use
ofmulti-/manycorearchitectures.Hencethisworkshop,“ApplicationsforMulti-
and Many-Core Processors”(A4MMC), which focuses entirely on application
case studies. With A4MMC, we aimed to provide a forum where multi- and
manycore application designers can exchange knowledge, insights and discover-
ies, and discuss their latest research advances. Further, by collocating A4MMC
with ISCA, we aimed to directly expose the software community’s findings, re-
quirements, and problems to a select audience of top computer architecture
researchers. This workshop provides room for the pull from the software side,
and offers an ideal opportunity for software and hardware researchers to com-
municate and debate on how to find the right balance between these two sides
of the“multicore revolution.”
Our finalgoalis to build a pool ofreal-lifemulticore applications,backedup
by performance studies and potential hardware add-ons. Such a collection will
be useful to both the hardware and software developers, and it will be a good
startingpoint for the tools and programmingmodels communities in their work
towardmore effective models and methods. We stronglybelieve this is the most
efficient way to bridge the multicore programmability gap in a systematic way.
Ana Lucia Varbanescu
Anca Molnos
Rob van Nieuwpoort