Computer Aided Design of Micro- And Nanoelectronic Devices

455 Pages·2016·15.92 MB·English

by  Chinmay Kumar Maiti

Computer Aided Design of
Micro- and Nanoelectronic
Devices
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Computer Aided Design of
Micro- and Nanoelectronic
Devices
Chinmay Kumar Maiti
Siksha ‘O’ Anusandhan University, India
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World Scientific
NEW JERSEY • LONDON • SINGAPORE • BEIJING • SHANGHAI • HONG KONG • TAIPEI • CHENNAI • TOKYO
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Published by
World Scientific Publishing Co. Pte. Ltd.
5 Toh Tuck Link, Singapore 596224
USA office: 27 Warren Street, Suite 401-402, Hackensack, NJ 07601
UK office: 57 Shelton Street, Covent Garden, London WC2H 9HE
Library of Congress Cataloging-in-Publication Data
Names: Maiti, C. K., author.
Title: Computer aided design of micro- and nanoelectronic devices / Chinmay Kumar Maiti,
Siksha 'O' Anusandhan University, India.
Description: [Hackensack] New Jersey : World Scientific, [2016] |
Includes bibliographical references and index.
Identifiers: LCCN 2016015379 | ISBN 9789814713078 (hc : alk. paper)
Subjects: LCSH: Electronic apparatus and appliances--Computer-aided design. |
Nanoelectromechanical systems--Design.
Classification: LCC TK7870 .M314 2016 | DDC 621.3810285--dc23
LC record available at https://lccn.loc.gov/2016015379
British Library Cataloguing-in-Publication Data
A catalogue record for this book is available from the British Library.
Copyright © 2017 by World Scientific Publishing Co. Pte. Ltd.
All rights reserved. This book, or parts thereof, may not be reproduced in any form or by any means,
electronic or mechanical, including photocopying, recording or any information storage and retrieval
system now known or to be invented, without written permission from the publisher.
For photocopying of material in this volume, please pay a copying fee through the Copyright Clearance
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is not required from the publisher.
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Desk Editor: V. Vishnu Mohan
Typeset by Stallion Press
Email: [email protected]
Printed in Singapore
Vishnu Mohan - Computer Aided Design.indd 1 10-06-16 2:08:44 PM
Dedication
In the loving memory of

Srimati Santilata Maiti

and

Srimati Bina Das

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Preface
The road towards enhancing the performance of integrated circuits
comprises fundamental improvement of the devices via new structures,
scaling the size and transistor features which increase its speed and
reduce power consumption. Combination of new device architectures
and use of strain-engineered materials have led towards nanoelectronic
devices and pushed the limits of CMOS and BiCMOS scaling. Typical
transistor gate lengths have reached 10 nm. The first processor built with
the 14 nm technology is the Intel Core-M processor. At the beginning of
2015, the fifth generation Intel Core processor was released, which is
also built with the 14 nm technology and with 1.3 billion transistors.

Computer aided design and simulation of transistors for upcoming
technology nodes are the main focus of this book. The monograph
address mainly the design issues of advanced CMOS and bipolar devices
with technical depth and conceptual clarity and presents leading-edge
device design solutions to address the new challenges presented by
advanced technology nodes. The device design examples covered in this
monograph are in use and provide useful technology and device physics
insights. The purpose of this monograph is also to bring into one
resource presenting a comprehensive perspective of advanced micro- and
nanoelectronic device design using advanced simulation tools.

One major limitation of currently available books in related areas is that
mostly the design and simulation results presented are using 2D
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simulators. Due to ultra-small size of the state-of-the-art devices, 3D
effects have become dominant. In order to achieve a better understanding
of simulated and fabricated device characteristics, 3D process/device
simulation is essential. Also 3D integration has become one of the main
directions to fit into device performance roadmaps.

vii
viii Preface

After a brief discussion on the basic device physics, the readers are
introduced to device design and simulation. Device design examples
considered are from various areas, viz., bipolar and CMOS technology,
memory and power devices, and solar cells. This monograph also
presents design, simulation and analysis of heterostructure silicon and
III-V compound semiconductor devices. Detailed and extensive
technology CAD simulations have been presented for stress- and strain-
engineered 3D FinFET devices. This monograph attempts to fill the gap
in the literature in a rapidly evolving field as it blends together a wide
ranging description of TCAD activities in process design to device
design to compact model generation in Si, SiGe and III-V materials,
technology, and their applications.

This monograph is primarily intended for senior undergraduate and
graduate students and professors who wish to find a technology CAD
teaching reference book and others who are interested in learning about
semiconductor device design using simulation. This monograph may be
used as a reference for engineers involved in advanced device and
process design. Technology CAD specialists may find this monograph
useful since it discusses the organization of TCAD simulation systems
and also presents many case studies where the reader may apply the
CAD tools in different situations. Approaches described in this
monograph are expected to boost advanced device design using
challenging TCAD simulations and help with characterizing new
processes and devices.

I am especially grateful to all my research students whose association has
been the source of learning for many new topics covered in this
monograph. Special thanks go to Dr. A. Bag, who has kindly contributed
a chapter (Chapter 13) on Heterojunction Solar Cells. We would also like
to express our deep appreciation to WSPC team (V. Vishnu Mohan and
Steven Patt). Finally, I would like to thank my family members (my wife
C Bhaswati, sons Ananda and Anindya) for their support, patience and

understanding during the preparation of the manuscript.

C. K. Maiti
SOA University,
Bhubaneswar
December 2015
List of Tables
Table 1.1. Scaling MOSFET device and circuit parameters.. ............................................. 2
Table 6.1. Material parameters of Ga In P used in GaInP/GaAs HBT device
0.51 0.49
simulations. Data source: Ioffe Physico-Technical Institute. “New
Semiconductor Materials Characteristics and Properties”.
http://www.ioffe.ru/.. .................................................................................. 166
Table 6.2. Material properties for Ga In P and GaAs. Data source: Ioffe
0.51 0.49
Physico-Technical Institute. “New Semiconductor Materials
Characteristics and Properties”. http://www.ioffe.ru/. ................................ 167
Table 6.3. Structure of GaInP/GaAs collector-up HBT used in simulation. Data
source: Ioffe Physico-Technical Institute. “New Semiconductor
Materials Characteristics and Properties”. http://www.ioffe.ru/.. ............... 169
Table 8.1. n-FinFET model geometry parameters. After B. Gaynor, Simulation of
FinFET electrical performance dependence on Fin shape and TSV and
back-gate noise coupling in 3D integrated circuits, PhD Thesis, Tufts
University, 2014. ........................................................................................ 226
Table 8.2. The FinFET parameters used in simulation. .................................................. 236
Table 13.1. Material parameters and device dimensions of β-FeSi and c-Si layer.
2
Data source: Ioffe Physico-Technical Institute. “New Semiconductor
Materials Characteristics and Properties”. http://www.ioffe.ru/.. ............... 377
Table 13.2. Parameters for defects modeling in amorphous FeSi . Data source:
2
C Ioffe Physico-Technical Institute. “New Semiconductor Materials
Characteristics and Properties”. http://www.ioffe.ru/.. ............................... 379
Table 13.3. Parameters for defects modeling at FeSi /Si interface. Data source:
2
Ioffe Physico-Technical Institute. “New Semiconductor Materials
Characteristics and Properties”. http://www.ioffe.ru/... .............................. 380
Table 14.1. Locally extracted parameters.. ..................................................................... 418
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List of Figures
Figure 1.1. Time evolution of MOSFET gate length in microprocessors. ITRS
roadmap projections show the gate length to scale down to around 8nm at
the end-of-roadmap. After V. Deshpande, Scaling beyond Moore: single
electron transistor and single atom transistor integration on CMOS, PhD
Thesis, University of Grenoble, 2012 .................................................................. 5
Figure 1.2. Recent MOSFET architectures and process nodes released by Intel
Corporation. After M. Koyama, Electrical characterization of interface
properties in nano-scaled MOSFET devices based on low-frequency
fluctuations, PhD Thesis, Universite Grenoble Alpes, 2015 ............................... 6
Figure 1.3. ITRS requirements for future high performance (HP) and low standby
power (LSTP) logic circuits consisting of MG FETs. (a) MOSFET gate
length Lg, and (b) circuit supply voltage Vd and MOSFET drain voltage
Vd are plotted as a function of year between 2015 and 2026 (Source:
ITRS 2013) .......................................................................................................... 7
Figure 1.4. Types of multiple gate MOSFETs. (a) SOI DG FinFET, (b) SOI tri-gate
FET, (c) SOI π-gate FET, (d) SOI Ω-gate FET, (d) SOI quadruple-GAA
FET, and (e) bulk tri-gate FET. After M. Koyama, Electrical
characterization of interface properties in nano-scaled MOSFET devices
based on low-frequency fluctuations, PhD Thesis, Universite Grenoble
Alpes, 2015 ......................................................................................................... 8
Figure 1.5. Schemes of front end stressors types. After V. Fiori, How do Mechanics
and Thermo mechanics affect microelectronic products: Some residual
stress and strain effects, investigations and industrial management, PhD
Thesis, Linstitut national des sciences appliquées de Lyon, 2010 ..................... 10
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Figure 1.6. Illustration of process-induced stress on Si MOSFETs. (a) Biaxial stress
caused from lattice mismatch between the Si channel and the relaxed SiGe
substrate. (b) Uniaxial stress induced by the nitride capping layer. After
M. Chu, Characterization and modeling of strained Si FET and GaN
HEMT devices, PhD Thesis, University of Florida, 2011 ................................. 11

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