Complementary metal oxide silicon cyclic redundancy check generators.

82 Pages·0.93 MB·en_US

by  Chin, Miao.;Yang, Chyan.;Loomis, H. H.

HHHhBHbS
IB
rata K££s!£
EE35
Ti m
MPAmHe
BBER9r99QD

NAVAL POSTGRADUATE SCHOOL
Monterey
California
,
THESIS
COMPLEMENTARY METAL OXIDE SILICON CYCLIC
REDUNDANCY CHECK GENERATORS
by
Chin, Miao
June 1991
Thesis Advisor: Chyan Yang
Approved for public release; distribution is unlimited.
T256812

Unclassified
Security Classification of this page
REPORT DOCUMENTATION PAGE
la Report Security Classification Unclassified 1b Restrictive Markings
2a Security Classification Authority 3 Distribution Availability of Report
2b Declassification/Downgrading Schedule Approved for public release; distribution is unlimited.
4 Performing Organization Report Number(s) 5 Monitoring Organization Report Numhcr(s)
6a Name of Performing Organization 6b Office Symbol 7a Name of Monitoring Organization
Naval Postgraduate School (IfApplicable) EC Naval Postgraduate School
6c Address (city,state, andZIPcode) 7b Address(city, stale, andZIPcode)
Monterey, CA 93943-5000 Monterey, CA 93943-5000
8a Name of Funding/Sponsoring Organization 8b Office Symbol 9 Procurement Instrument Identification Number
(7/Applicable)
8c Address (city, stale, andZIPcode) 1 SourceofFunding Numbers
Program ElementNumber ProjectNo | TiskNo | WorkUnitAccessionNo
1 1 Title (Include Security Classification)
COMPLEMENTARY METAL OXIDE SILICON CYCLIC REDUNDANCY CHECK GENERATORS
12 Personal Author(s)
Chin, Miao
13a Type of Report 13b TimeCovered 14 Date of Report(year, month.day) 15 Page Count
Master's Thesis From To Junel991 71
16 SupplementaryNotation The views expressed in this thesis are those of the author and do not reflect the official
policy orposition ofthe Department ofDefense or the U.S. Government.
17 Cosati Codes 18 Subject Terms (continue on reverse ifnecessary and identify by block number)
Field Group Subgroup Cyclic Redundancy Check; Linear Feedback Shift Register; Built-in SelfTest;
Design for Testability; Level Sensitive Scan Design; Circuit UnderTest; Weighted
Pseudorandom Pattern Generator, Very Large Scale Integrated Circuits, VLSI.
19 Abstract (continue on reverse ifnecessary and identify by block number
This thesis introduces an economical way ofimplementing the test pattern generation for built-in test. A layout
generator as well as a netlist generator are written and validated. In addition, we use the netlist generator to
investigate the properties ofnonprimitive polynomials.
20 Distribution/Availability of Abstract 21 Abstract Security Classification
X| unclassified/unlimited same as report DTICusers Unclassified
I
22a Name of Responsible Individual 22b Telephone(IncludeAreacode) 22c Office Symbol
Yang, Chyan [phone] EC/Ya
DD FORM 1473. 84 MAR 83 APR edition may be used until exhausted security classification of this page
All other editions are obsolete Unclassified
Approved for public release; distribution is unlimited.
Complementary Metal Oxide Silicon Cyclic Redundancy
Check Generators
by
Chin, Miao
Commander, Republic of China Navy
B.S., Chinese Naval Academy, 1978
Submitted in partial fulfillment of the requirements
for the degree of
MASTER OF SCIENCE IN ENGINEERING SCIENCE
from the
NAVAL POSTGRADUATE SCHOOL
June 1991
Michael A. Morgan, Chairman
Department of Electrical and Computer Engineering
11
ABSTRACT
This thesis introduces an economical way of implementing the test
A
pattern generation for built-in test. layout generator as well as a netlist
generator are written and validated. In addition, we use the netlist generator
to investigate the properties of nonprimitive polynomials.
in
TABLE OF CONTENTS
L INTRODUCTION 1
D. BUILT-IN SELF TEST 3
A. DESIGN FOR TESTABILITY 3
B. BUILT-IN TEST 4
C TEST GENERATION 6
CRC AND PRPG GENERATORS
IE. 10
A. OVERVIEW OF CYCLE REDUNDANCY CODE (CRC) 10
CRC DIVIDER
B. 11
C PSEUDORANDOM PATTERN GENERATOR
15
D. NETLIST GENERATOR FOR CRC DIVIDERS 18
CRC LAYOUT GENERATOR
E. 19
IV. WEIGHTED PRPG 22
A. OVERVIEW OF WPRPG 22
B. SIGNAL PROBABILITY 23
C TWO EXPERIMENTS 25
WPRPG
1. Netlist Simulation 25
2. Circuit Layout 25
V CONCLUSIONS
29
APPENDIX A
31
APPENDIX B 50
APPENDIX C
53
LIST OF REFERENCES 61
INITIAL DISTRIBUTION LIST 63
IV