Table Of ContentK11940_cover.fhmx 2/2/11 2:01 PM Page 1
C M Y CM MY CY CMY K
COMPUTER ENGINEERING AAyyaallaa
CC
OO
MM
COMMUNICATION ARCHITECTURES FOR
MM
SYSTEMS-ON-CHIP UU
NN
II
CC
AA
A presentation of state-of-the-art approaches from an industrial TT
II
applications perspective, Communication Architectures for Systems- OO
on-Chip shows professionals, researchers, and students how to NN
attack the problem of data communication in the manufacture of A A
SoC architectures. RR
CC
With its lucid illustration of current trends and research improving HH
II
the performance, quality, and reliability of transactions, this is TT
an essential reference for anyone dealing with communication EE
CC
mechanisms for embedded systems, systems-on-chip, and multi-
TT
processor architectures—or trying to overcome existing limitations. UU
RR
Exploring architectures currently implemented in manufactured
EE
SoCs—and those being proposed—this book analyzes a wide range SS
of applications, including
FF
OO
• Well-established communication buses
RR
• Less common networks-on-chip
SS
• Modern technologies that include the use of carbon nanotubes YY
(CNTs) SS
TT
• Optical links used to speed up data transfer and boost both EE
security and quality of service (QoS) MM
SS
The book’s contributors pay special attention to newer problems, --
OO
including how to protect transactions of critical on-chip information
NN
(personal data, security keys, etc.) from an external attack. They --
examine mechanisms, revise communication protocols involved, CC
HH
and analyze overall impact on system performance.
II
PP
K11940
66000000 BBrrookkeenn SSoouunndd PPaarrkkwwaayy,, NNWW ISBN: 978-1-4398-4170-9
SSuuiittee 330000,, BBooccaa RRaattoonn,, FFLL 3333448877 90000
227700 MMaaddiissoonn AAvveennuuee
aann iinnffoorrmmaa bbuussiinneessss NNeeww YYoorrkk,, NNYY 1100001166
wwwwww..ccrrccpprreessss..ccoomm 22 PPaarrkk SSqquuaarree,, MMiillttoonn PPaarrkk
AAbbiinnggddoonn,, OOxxoonn OOXX1144 44RRNN,, UUKK 9 781439 841709
COMMUNICATION
ARCHITECTURES FOR
SYSTEMS-ON-CHIP
Embedded Systems
Series Editor
Richard Zurawski
SA Corporation, San Francisco, California, USA
Communication Architectures for Systems-on-Chip, edited by José L. Ayala
Real Time Embedded Systems Design and Analysis with Open-Source Operating
Systems, Ivan Cibrario Bertolotti and Gabriele Manduchi
Time-Triggered Communication, edited by Roman Obermaisser
COMMUNICATION
ARCHITECTURES FOR
SYSTEMS-ON-CHIP
Edited by
José L. Ayala
Boca Raton London New York
CRC Press is an imprint of the
Taylor & Francis Group, an informa business
CRC Press
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© 2011 by Taylor & Francis Group, LLC
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No claim to original U.S. Government works
Version Date: 20111012
International Standard Book Number-13: 978-1-4398-4171-6 (eBook - PDF)
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Dedicado a quien me ensen˜a cada d´ıa,
a quien me hace pensar,
a quien me sonr´ıe y me apoya,
a quien me estimula y causa admiraci´on.
Dedicado a ti.
TThhiiss ppaaggee iinntteennttiioonnaallllyy lleefftt bbllaannkk
Contents
List of Figures xv
List of Tables xxiii
Preface xxv
Acknowledgments xxvii
Author xxix
1 Introduction 1
Jos´e L. Ayala
1.1 Today’s Market for Systems-on-Chip . . . . . . . . . . . . . 1
1.2 Basics of the System-on-Chip Design . . . . . . . . . . . . . 3
1.2.1 Main Characteristics of the Design Flow . . . . . . . . 4
1.2.1.1 Interoperability . . . . . . . . . . . . . . . . 4
1.2.2 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.3 Power Consumption . . . . . . . . . . . . . . . . . . . 5
1.2.4 Security . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.5 Limitations of the Current Engineering Practices for
System-on-Chip Design . . . . . . . . . . . . . . . . . 7
1.3 Open Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.6 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Communication Buses for SoC Architectures 15
Pablo Garc´ıa del Valle and Jos´e L. Ayala
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.1 Current Research Trends . . . . . . . . . . . . . . . . 17
2.1.2 Modeling and Exploring the Design Space of On-Chip
Communication . . . . . . . . . . . . . . . . . . . . . . 18
2.1.3 Automatic Synthesis of Communication Architectures 18
2.2 The AMBA Interface . . . . . . . . . . . . . . . . . . . . . . 19
2.2.1 AMBA 4 AXI Interface: AXI4 . . . . . . . . . . . . . 21
2.2.1.1 AXI4-Lite. . . . . . . . . . . . . . . . . . . . 22
2.2.1.2 AXI4-Stream . . . . . . . . . . . . . . . . . . 22
2.2.2 AMBA 3 AHB Interface . . . . . . . . . . . . . . . . . 22
vii
viii Contents
2.2.2.1 AMBA 3 AHB-Lite . . . . . . . . . . . . . . 24
2.2.2.2 Multilayer AHB Interface . . . . . . . . . . . 25
2.2.3 AMBA 3 APB Interface . . . . . . . . . . . . . . . . . 26
2.2.4 AMBA 3 ATB Interface . . . . . . . . . . . . . . . . . 27
2.2.5 AMBA Tools . . . . . . . . . . . . . . . . . . . . . . . 28
2.2.5.1 ARM’s CoreLink . . . . . . . . . . . . . . . . 28
2.2.5.2 ARM’s CoreSight . . . . . . . . . . . . . . . 30
2.2.5.3 Third-Party Tools . . . . . . . . . . . . . . . 30
2.3 Sonics SMART Interconnects . . . . . . . . . . . . . . . . . . 30
2.3.1 SNAP: Sonics Network for AMBA Protocol . . . . . . 32
2.3.2 SonicsSX Interconnect . . . . . . . . . . . . . . . . . . 33
2.3.3 SonicsLX Interconnect . . . . . . . . . . . . . . . . . . 33
2.3.4 SonicsMX Interconnect . . . . . . . . . . . . . . . . . 34
2.3.5 S3220 Interconnect . . . . . . . . . . . . . . . . . . . . 34
2.3.6 Sonics Tools. . . . . . . . . . . . . . . . . . . . . . . . 36
2.3.6.1 SonicsStudio . . . . . . . . . . . . . . . . . . 36
2.3.6.2 SNAP Capture Tool . . . . . . . . . . . . . . 38
2.4 CoreConnect Bus . . . . . . . . . . . . . . . . . . . . . . . . 38
2.4.1 Processor Local Bus (PLB) . . . . . . . . . . . . . . . 42
2.4.1.1 PLB6 . . . . . . . . . . . . . . . . . . . . . . 42
2.4.2 On-Chip Peripheral Bus (OPB) . . . . . . . . . . . . . 43
2.4.3 Device Control Register Bus (DCR) . . . . . . . . . . 43
2.4.4 Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.4.4.1 PLB-OPB Bridges . . . . . . . . . . . . . . . 44
2.4.4.2 AHB Bridges . . . . . . . . . . . . . . . . . . 44
2.4.5 Coreconnect Tools . . . . . . . . . . . . . . . . . . . . 45
2.4.5.1 Design Toolkits . . . . . . . . . . . . . . . . 45
2.4.5.2 PLB Verification: PureSpec . . . . . . . . . . 46
2.5 STBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.5.1 STBus Verification Tools . . . . . . . . . . . . . . . . 49
2.5.2 Towards NoC . . . . . . . . . . . . . . . . . . . . . . . 50
2.6 FPGA On-Chip Buses . . . . . . . . . . . . . . . . . . . . . . 50
2.6.1 Altera: Avalon . . . . . . . . . . . . . . . . . . . . . . 51
2.6.2 Xilinx . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.6.2.1 IBM’s CoreConnect . . . . . . . . . . . . . . 51
2.6.2.2 Extensible Processing Platform . . . . . . . . 52
2.7 Open Standards . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.7.1 Introducing the OCP-IP . . . . . . . . . . . . . . . . . 55
2.7.2 Specification . . . . . . . . . . . . . . . . . . . . . . . 56
2.7.3 Custom Cores. . . . . . . . . . . . . . . . . . . . . . . 58
2.7.4 Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.7.4.1 CoreCreator . . . . . . . . . . . . . . . . . . 60
2.7.4.2 OCP SystemC TLM Kit . . . . . . . . . . . 62
2.7.4.3 OCP Conductor . . . . . . . . . . . . . . . . 62
2.8 Wishbone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Contents ix
2.8.1 The Wishbone Bus Transactions . . . . . . . . . . . . 64
2.9 Other Specific Buses . . . . . . . . . . . . . . . . . . . . . . . 64
2.9.1 Automotive . . . . . . . . . . . . . . . . . . . . . . . . 65
2.9.2 Avionics . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.9.2.1 Military . . . . . . . . . . . . . . . . . . . . . 68
2.9.2.2 Civil. . . . . . . . . . . . . . . . . . . . . . . 68
2.9.2.3 Debugging in Avionics. . . . . . . . . . . . . 70
2.9.3 Home Automation . . . . . . . . . . . . . . . . . . . . 70
2.10 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.11 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.12 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
2.13 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3 NoC Architectures 83
Martino Ruggiero
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.2 Advantages of the NoC Paradigm . . . . . . . . . . . . . . . 85
3.3 Challenges of the NoC Paradigm . . . . . . . . . . . . . . . . 87
3.4 Principles of NoC Architecture . . . . . . . . . . . . . . . . . 88
3.4.1 Topology . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.4.2 Routing . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.4.2.1 Oblivious Routing Algorithms . . . . . . . . 94
3.4.2.2 Deterministic Routing Algorithms . . . . . . 97
3.4.2.3 Adaptive Routing Algorithms . . . . . . . . 99
3.4.2.4 Problems on Routing . . . . . . . . . . . . . 101
3.4.3 Flow Control . . . . . . . . . . . . . . . . . . . . . . . 101
3.4.3.1 Message-Based . . . . . . . . . . . . . . . . . 102
3.4.3.2 Packet-Based . . . . . . . . . . . . . . . . . . 103
3.4.3.3 Flit-Based . . . . . . . . . . . . . . . . . . . 103
3.5 Basic Building Blocks of a NoC . . . . . . . . . . . . . . . . 104
3.5.1 Router . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
3.5.1.1 Virtual Channels . . . . . . . . . . . . . . . . 105
3.5.2 Network Interface . . . . . . . . . . . . . . . . . . . . 105
3.5.3 Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
3.6 Available NoC Implementations and Solutions . . . . . . . . 106
3.6.1 IBM Cell . . . . . . . . . . . . . . . . . . . . . . . . . 106
3.6.1.1 Element Interconnect Bus . . . . . . . . . . . 107
3.6.2 Intel TeraFLOPS . . . . . . . . . . . . . . . . . . . . . 108
3.6.2.1 TeraFLOPSNetwork . . . . . . . . . . . . . 109
3.6.3 RAW Processor . . . . . . . . . . . . . . . . . . . . . . 109
3.6.4 Tilera Architectures . . . . . . . . . . . . . . . . . . . 110
3.6.4.1 iMesh . . . . . . . . . . . . . . . . . . . . . . 112
3.6.5 Intel Single-Chip Cloud Computer . . . . . . . . . . . 112
3.6.6 ST Microelectronics STNoC . . . . . . . . . . . . . . . 114
3.6.7 Xpipes . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
