CMOS Sigma-Delta Converters: Practical Design Guide

420 Pages·2013·15.13 MB·English

CMOS SIGMA-DELTA
CONVERTERS
CMOS SIGMA-DELTA
CONVERTERS
PRACTICAL DESIGN GUIDE
Jose´ M. de la Rosa and Roc´ıo del R´ıo
UniversityofSeville,Spain
A John Wiley & Sons, Ltd., Publication
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LibraryofCongressCataloging-in-PublicationData
Rosa,JoseM.dela.
CMOSsigma-deltaconverters:practicaldesignguide/JoseM.delaRosaand
RociodelRio.
pagescm
Includesbibliographicalreferencesandindex.
ISBN978-1-119-97925-8(hardback:alk.paper)—ISBN978-1-118-56922-1
(ebook/epdf)—ISBN978-1-118-56843-9(epub)—ISBN978-1-118-56842-2(mobi)—
ISBN978-1-118-56923-81.Metaloxidesemiconductors,Complementary—Designand
construction.I.Title.
TK7871.99.M44R6682013
621.3815(cid:2)9—dc23
2012041956
AcataloguerecordforthisbookisavailablefromtheBritishLibrary.
ISBN:978-1-119-97925-8
Setin10/12ptTimesbyLaserwordsPrivateLimited,Chennai,India
This book is dedicated to the memory of my son Jose´ Manuel
Jose´ M. de la Rosa
To my wife Visi, my daughter Mar´ıa, my son Jaime,
my parents Carmen and Juan, and my parents-in-law
Mar´ıa Luisa and Jose´ Antonio
Jose´ M. de la Rosa
To my husband Juanan and my son Mario
Roc´ıo del R´ıo
“If you love what you do and are willing to do what it takes,
it’s within your reach. And it’ll be worth every minute you
spend alone at night, thinking and thinking about what it is
you want to design or build. It’ll be worth it, I promise.”
Steve Wozniak (iWoz, 2006)
Contents
List of Abbreviations xvii
Preface xxi
Acknowledgements xxvii
1 Introduction to (cid:1)(cid:2) Modulators: Basic Concepts
and Fundamentals 1
1.1 Basics of A/D Conversion 2
1.1.1 Sampling 2
1.1.2 Quantization 3
1.1.3 Quantization White Noise Model 4
1.1.4 Noise Shaping 7
1.2 Basics of Sigma-Delta Modulators 8
1.2.1 Topology of (cid:1)(cid:2) ADCs 8
1.2.2 Signal Processing in (cid:1)(cid:2)Ms 9
1.2.3 Performance Metrics of (cid:1)(cid:2)Ms 10
1.2.4 Performance Enhancement of (cid:1)(cid:2)Ms 13
1.3 Classification of (cid:1)(cid:2) Modulators 15
1.4 Single-Loop (cid:1)(cid:2) Modulators 16
1.4.1 Second-Order (cid:1)(cid:2)M 16
1.4.2 High-Order (cid:1)(cid:2)Ms 20
1.5 Cascade (cid:1)(cid:2) Modulators 24
1.6 Multibit (cid:1)(cid:2) Modulators 29
1.6.1 Influence of Multibit DAC Errors 30
1.6.2 DEM Techniques 31
1.6.3 Dual Quantization 34
1.7 Band-Pass (cid:1)(cid:2) Modulators 36
1.7.1 The z→−z2 LP–BP Transformation 37
1.7.2 BP-(cid:1)(cid:2)Ms with Optimized NTF 39
1.8 Continuous-Time (cid:1)(cid:2) Modulators 41
1.8.1 DT–CT Transformation of (cid:1)(cid:2)Ms 44
1.8.2 Direct Synthesis of CT-(cid:1)(cid:2)Ms 48
xii Contents
1.9 Summary 49
References 49
2 Circuits and Errors: Systematic Analysis and Practical Design Issues 54
2.1 Nonidealities in Switched-Capacitor (cid:1)(cid:2) Modulators 55
2.2 Finite Amplifier Gain in SC-(cid:1)(cid:2)Ms 56
2.3 Capacitor Mismatch in SC-(cid:1)(cid:2)Ms 60
2.4 Integrator Settling Error in SC-(cid:1)(cid:2)Ms 62
2.4.1 Behavioral Model for the Integrator Settling 62
2.4.2 Linear Effect of Finite Amplifier Gain-Bandwidth Product 67
2.4.3 Nonlinear Effect of Finite Amplifier Slew Rate 68
2.4.4 Effect of Finite Switch On-Resistance 69
2.5 Circuit Noise in SC-(cid:1)(cid:2)Ms 71
2.6 Clock Jitter in SC-(cid:1)(cid:2)Ms 75
2.7 Sources of Distortion in SC-(cid:1)(cid:2)Ms 76
2.7.1 Nonlinear Amplifier Gain 77
2.7.2 Nonlinear Switch On-Resistance 78
2.8 Nonidealities in Continuous-Time (cid:1)(cid:2) Modulators 80
2.9 Clock Jitter in CT-(cid:1)(cid:2)Ms 81
2.9.1 Jitter in Return-to-Zero DACs 82
2.9.2 Jitter in NonReturn-to-Zero DACs 83
2.9.3 Jitter in Switched-Capacitor DACs 84
2.10 Excess Loop Delay in CT-(cid:1)(cid:2)Ms 85
2.11 Quantizer Metastability in CT-(cid:1)(cid:2)Ms 88
2.12 Finite Amplifier Gain in CT-(cid:1)(cid:2)Ms 89
2.13 Time-Constant Error in CT-(cid:1)(cid:2)Ms 92
2.14 Finite Integrator Dynamics in CT-(cid:1)(cid:2)Ms 94
2.15 Circuit Noise in CT-(cid:1)(cid:2)Ms 95
2.16 Sources of Distortion in CT-(cid:1)(cid:2)Ms 97
2.16.1 Nonlinearities in the Front-End Integrator 97
2.16.2 Intersymbol Interference in the Feedback DAC 98
2.17 Case Study: High-Level Sizing of a (cid:1)(cid:2)M 99
2.18 Summary 107
References 107
3 Behavioral Modeling and High-Level Simulation 110
3.1 Systematic Design Methodology of (cid:1)(cid:2) Modulators 110
3.1.1 System Partitioning and Abstraction Levels 110
3.1.2 Sizing Process 112
3.2 Simulation Approaches for the High-Level Evaluation of (cid:1)(cid:2)Ms 113
3.2.1 Alternatives to Transistor-Level Simulation 114
3.2.2 Event-Driven Behavioral Simulation Technique 116
3.2.3 Programming Languages and Behavioral Modeling Platforms 117
3.3 Implementing (cid:1)(cid:2)M Behavioral Models 118
3.3.1 From Circuit Analysis to Computational Algorithms 118
3.3.2 Time-Domain versus Frequency-Domain Behavioral Models 121
Contents xiii
3.3.3 Implementing Time-Domain Behavioral Models in MATLAB 124
3.3.4 Building Time-Domain Behavioral Models as SIMULINK
C-MEX S-Functions 128
3.4 Efficient Behavioral Modeling of (cid:1)(cid:2)M Building Blocks using
C-MEX S-Functions 134
3.4.1 Modeling of SC Integrators using S-Functions 134
3.4.2 Modeling of CT Integrators using S-Functions 148
3.4.3 Behavioral Modeling of Quantizers using S-Functions 153
3.5 SIMSIDES: A SIMULINK-Based Behavioral Simulator for (cid:1)(cid:2)Ms 159
3.5.1 Model Libraries Included in SIMSIDES 159
3.5.2 Structure of SIMSIDES and User Interface 163
3.6 Using SIMSIDES for the High-Level Sizing and Verification
of (cid:1)(cid:2)Ms 167
3.6.1 SC Second-Order Single-Bit (cid:1)(cid:2)M 168
3.6.2 CT Fifth-Order Cascade 3-2 Multibit (cid:1)(cid:2)M 177
3.7 Summary 183
References 184
4 Circuit-Level Design, Implementation, and Verification 186
4.1 Macromodeling (cid:1)(cid:2)Ms 186
4.1.1 SC Integrator Macromodel 187
4.1.2 CT Integrator Macromodel 189
4.1.3 Nonlinear OTA Transconductor 191
4.1.4 Embedded Flash ADC Macromodel 191
4.1.5 Feedback DAC Macromodel 192
4.1.6 Examples of (cid:1)(cid:2)M Macromodels 195
4.2 Including Noise in Transient Electrical Simulations of (cid:1)(cid:2)Ms 199
4.2.1 Generating and Injecting Noise Data Sequences in HSPICE 201
4.2.2 Analyzing the Impact of Main Noise Sources in SC Integrators 203
4.2.3 Generating and Injecting Flicker Noise Sources in
Electrical Simulations 204
4.2.4 Test Bench to Include Noise in the Simulation of(cid:1)(cid:2)Ms 207
4.3 Processing (cid:1)(cid:2)M Output Results of Electrical Simulations 208
4.4 Design Considerations and Simulation Test Benches
of (cid:1)(cid:2)M Basic Building Blocks 213
4.4.1 Design Considerations of CMOS Switches 214
4.4.2 Design Considerations of Operational Amplifiers 222
4.4.3 Design Considerations of Transconductors 230
4.4.4 Design Considerations of Comparators 236
4.4.5 Design Considerations of Current-Steering DACs 242
4.5 Auxiliary (cid:1)(cid:2)M Building Blocks 250
4.5.1 Clock-Phase Generators 250
4.5.2 Generation of Common-Mode Voltage, Reference Voltage,
and Bias Currents 253
4.5.3 Additional Digital Logic 256
xiv Contents
4.6 Layout Design, Floorplanning, and Practical Issues 257
4.6.1 Layout Floorplanning 257
4.6.2 I/O Pad Ring 259
4.6.3 Importance of Layout Verification and Catastrophic Failures 261
4.7 Chip Package, Test PCB, and Experimental Set-Up 263
4.7.1 Bonding Diagram and Package 264
4.7.2 Test PCB 264
4.7.3 Experimental Test Set-Up 266
4.8 Summary 270
References 270
5 Frontiers of (cid:1)(cid:2) Modulators: Trends and Challenges 273
5.1 Overview of the State of the Art on (cid:1)(cid:2)Ms 274
5.1.1 DR-versus-B Conversion Region 286
w
5.1.2 Conversion Energy and Figures of Merit 287
5.2 Empirical and Statistical Analysis of State-of-the-Art (cid:1)(cid:2)Ms 291
5.2.1 SC versus CT State-of-the-Art (cid:1)(cid:2)Ms 291
5.2.2 Gm-C versus Active-RC State-of-the-Art CT-(cid:1)(cid:2)Ms 292
5.2.3 Technology Used in State-of-the-Art (cid:1)(cid:2)Ms 295
5.2.4 Single-Loop versus Cascade State-of-the-Art (cid:1)(cid:2)Ms 295
5.2.5 Single-Bit versus Multibit State-of-the-Art(cid:1)(cid:2)Ms 296
5.2.6 Low-Pass versus Band-Pass State-of-the-Art(cid:1)(cid:2)Ms 299
5.3 Cutting-Edge (cid:1)(cid:2)M Architectures and Techniques 300
5.3.1 SMASH (cid:1)(cid:2)M Architectures 301
5.3.2 Hybrid (cid:1)(cid:2)Ms 304
5.3.3 Multirate (cid:1)(cid:2)Ms 307
5.3.4 Multibit (cid:1)(cid:2)Ms with Time-Coded Quantization 310
5.3.5 Mostly Digital (cid:1)(cid:2)Ms 311
5.3.6 Adaptive/Reconfigurable (cid:1)(cid:2)Ms 314
5.3.7 Ultra-High-Speed CT-(cid:1)(cid:2)Ms for RF Digitization 315
5.4 Classification of State-of-the-Art References 319
5.5 Summary 319
References 320
A SIMSIDES User Guide 334
A.1 Getting Started: Installing and Running SIMSIDES 334
A.2 Building and Editing (cid:1)(cid:2)M Architectures in SIMSIDES 335
A.3 Analyzing (cid:1)(cid:2)Ms in SIMSIDES 337
A.4 Example 345
A.5 Getting Help 354
B SIMSIDES Block Libraries and Models 355
B.1 Overview of SIMSIDES Libraries 355
B.2 Ideal Libraries 355
B.2.1 Ideal Integrators 355
B.2.2 Ideal Resonators 357