CMOS RF Power Amplifiers

131 Pages·2011·3.53 MB·English

by  Kim, Eung Jung

Highly Efficient Dynamic Supply Modulator for

Mobile Communication Systems

A Dissertation
Presented to
The Academic Faculty

By

Eung Jung Kim

In Partial Fulfillment
of the Requirements for the Degree
Doctor of Philosophy in the
School of Electrical and Computer Engineering

Georgia Institute of Technology
Atlanta, GA 30332

August, 2011
Highly Efficient Dynamic Supply Modulator for

Mobile Communication Systems

Approved by:

Dr. Kevin Kornegay, Advisor Dr. Shyh-Chiang Shen
School of Electrical and Computer School of Electrical and Computer
Engineering Engineering
Georgia Institute of Technology Georgia Institute of Technology

Dr. Jong-Man Kim Dr. Jun-Hee Heu
School of Electrical and Computer School of Electrical Engineering
Engineering Seoul National University
Georgia Institute of Technology

Dr. Chang-Ho Lee
Samsung Design Center Date Approved : April, 2011
Acknowledgements

First of all, I would like to acknowledge his great support and supervision of my
research advisor, Professor Kevin Kornegay. I am also grateful to all the committee
members, Professor Jongman Kim, Professor Shyh-Chiang Shen, Professor Chang-
Ho Lee, and Dr. Jun-Hee Hue for their time and effort in reviewing my dissertation
and serving as my defense committee members. I would like to specially express my
gratitude to Dr. Joy Laskar and Dr. Chang-Ho Lee for their great support and
guidance throughout this research.
I would also like to thank Dr. Changhyuk Cho and Dr. Woonyun Kim for their
technical guidance and assistance. I am thankful to my colleague members in
Microwave Application Group for their invaluable support and technical discussion.
Most of all, I am especially grateful to my parents and wife for their unconditional
love and support. All the credits for whatever I have accomplished go to my parents
for their endless support, insurmountable belief in my abilities. Without their support,
I would not have been keeping me motivated and focused. I cannot express my love
and gratitude enough to my wife for her never-end support throughout my life.
Without her encouragement and support, I would not be able to complete this work.
At the same token, I wish to thank all the other family members and friends
whose prayers and blessings have always helped me overcome many hurdles during
the course of this graduate research.

III
Table of Contents

Acknowledgements ................................................................................... III
List of Tables ......................................................................................... VIII
List of Figures ........................................................................................... IX
Glossary ................................................................................................. XIV
Summary ................................................................................................ XVI

Chapter 1
Introduction .................................................................................................1
1.1 Background ....................................................................................................... 1
1.2 Motivations........................................................................................................ 4

Chapter 2
Efficient RF Transmitter Design .................................................................7
2.1 Challenges in Efficient Transmitter Design ...................................................... 7
2.1.1 Limiting Factors to the Efficient RF Transmitter Design ......................... 7
2.2 Limiting Factors in a Static Power Supply...................................................... 12
2.2.1 Linear Regulators .................................................................................... 12
2.2.2 Switching Regulators .............................................................................. 13
IV
2.3 Efficiency Improvement Techniques for Linear Transmitters ........................ 15
2.3.1 Adaptive Gate-Bias Voltage Control ...................................................... 15
2.3.2 Envelope-Tracking Systems .................................................................... 16
2.3.3 Average Power Tracking System ............................................................ 18
2.3.4 Envelope Elimination and Restoration and Polar Modulation ................ 19
2.3.5 Various Topologies for a Dynamic Supply Modulator ........................... 21
2.4 Conclusion ....................................................................................................... 22

Chapter 3
Designing Synchronous Step-down Converter in Voltage-mode PWM
Control ............................................................................................ 23
3.1 Pulse Width Modulation (PWM) in Voltage Mode Control ............................. 23
3.1.1 Steady-State Analysis and Small Signal Model ......................................... 27
3.2 Selection of Power Inductor and Load Capacitor ............................................. 35
3.3 Circuit Topology and Operation ....................................................................... 36
3.3.1 Dead-time Control ...................................................................................... 36
3.3.2 Gate Driving Circuit and Power Transistor................................................ 37
3.3.3 Reference Generation ................................................................................. 40
3.3.4 Error Amplifier Design .............................................................................. 46
3.3.5 PWM Comparator ...................................................................................... 48
3.3.6 Adjustable Triangular Ramp Signal Generator .......................................... 52

V
Chapter 4
Switching-Frequency Modulation for Spurious-noise Reduction in a DC-
to-DC Converter for RF Power Amplifier ................................. 55
4.1 Overview ......................................................................................................... 56
4.2 Analysis ........................................................................................................... 58
4.3 Achieving Spread Spectrum ............................................................................ 62
4.4 Experimental Results....................................................................................... 68

Chapter 5
Average Inductor-Current-Sensing Circuit ............................................... 73
5.1 Overview ......................................................................................................... 73
5.2 Simulation Results........................................................................................... 77
5.3 Conclusion ....................................................................................................... 79

Chapter 6
Parallel Connected Dual Switching Converter ......................................... 80
6.1 Overview ......................................................................................................... 80
6.2 Circuit Implementation ................................................................................... 84
6.2.1 Design Voltage Mode Control Loop .......................................................... 84
6.2.2 Floor Plan ................................................................................................... 86
6.2.3 Layout......................................................................................................... 90
6.2.4 PCB Design ................................................................................................ 92
VI
6.3 Simulation Results........................................................................................... 93
6.4 Experimental Results....................................................................................... 98
6.5 Conclusions ................................................................................................... 102

Chapter 7
Conclusions ............................................................................................. 104
7.1 Challenges ..................................................................................................... 104
7.2 Technical Contributions and Impacts of the Dissertation ............................. 105
7.3 Future Work .................................................................................................. 106
References ................................................................................................ 107
Vita….. ..................................................................................................... 114

VII
List of Tables

Table 1. Modulation standards used in mobile communication devices [1] ................. 2
Table 2. Comparison of published envelope amplifiers .............................................. 22
Table 3. Error amplifier specifications compliance matrix. ........................................ 47
Table 4. PWM comparator specifications compliance matrix. ................................... 50
Table 5. Frequency changes in the frequency of the triangular ramp signal. ............. 54
Table 6. Switching frequency and output current of the fast and slow converter ....... 82
Table 7. Summary of the integrated dual converter’s experimental results. ............. 103

V III
List of Figures

Figure 1. Evolution of wireless communication Systems. ............................................ 1
Figure 2. Comparison of linear operation with a fixed-gain for envelope varying
signals and compressed operation with a variable gain for constant envelope
signals..................................................................................................................... 4
Figure 3. Variation of efficiency with output power for various amplifier
configurations and the output power probability distribution for CDMA signals. 8
Figure 4. Illustration of an amplitude-modulated waveform in a time domain. ......... 10
Figure 5. Output power distribution for CDMA modulation under short and long time
variations. ............................................................................................................. 11
Figure 6. Schematic of a typical linear regulator. ....................................................... 12
Figure 7. Schematic of a typical step-down switching regulator. ............................... 14
Figure 8. Simplified PA model with adaptive gate biasing control. ........................... 16
Figure 9. Schematic of a typical envelope tracking system. ....................................... 17
Figure 10. Schematic of (a) an envelope elimination and restoration (EER) system
and (b) a polar modulation transmitter. ................................................................ 20
Figure 11. Voltage-mode PWM controlled, step-down DC-to-DC converter. ........... 23
Figure 12. Cross-sectional view of a NMOS transistor (a) in a standard CMOS
process (b) in a triple-well CMOS process with a deep n-well layer. ................. 25
Figure 13. Voltage and current waveforms of a voltage-mode PWM controlled, step-
down DC-to-DC converter. .................................................................................. 26
IX
Figure 14. Diagram for a voltage-mode PWM controlled, step-down DC-to-DC
converter............................................................................................................... 28
Figure 15. Different types of loop filter for phase boosting. ...................................... 30
Figure 16. (a) Type-III loop filter and its Transfer function (b) frequency locations of
poles and zeros for type-III Loop Filter. .............................................................. 30
Figure 17. Frequency response of a type-III loop filter. ............................................. 31
Figure 18. Ripple voltage with a finite capacitance at the output LC-filter. ............... 34
Figure 19. Dead-time control logic circuit. ................................................................. 37
Figure 20. Schematic of the power transistors and their gate driving circuits. ........... 38
Figure 21. Waveform of the gate voltage in NMOS and PMOS power transistors with
dead-time control. ................................................................................................ 40
Figure 22. Conceptual schematic for a bandgap reference circuit. ............................. 41
Figure 23. Block diagram of the proposed reference generation circuit. ................... 44
Figure 24. Simulated results for (a) start-up of the reference generation circuit (b)
characteristics of the bandgap reference voltage and the 3.0 volt regulated
voltage output. ...................................................................................................... 45
Figure 25. Schematic of the error amplifier. ............................................................... 47
Figure 26. Open-loop gain and phase of the error amplifier when the input common
level is varied from 0.1 V to 2.5 V ....................................................................... 48
Figure 27. Schematic of a high-gain, open-loop comparator with internal positive
feedback for hysteresis transfer curve. ................................................................. 50
Figure 28. (a) Comparator transfer curve and transient response to a noisy input (b)
simulated comparator transfer curve indicating trip points with hysteresis......... 51
X