CMOS Analog and Radio-Frequency Integrated-Circuit Design Employing Low-Power Switched ...

195 Pages·2011·1.83 MB·English

CMOS Analog and Radio-Frequency Integrated-Circuit Design
Employing Low-Power Switched-Capacitor Techniques

by

Yu Song

Submitted in Partial Fulfillment
of the
Requirements for the Degree
Doctor of Philosophy

Supervised by
Professor Zeljko Ignjatovic
Department of Electrical and Computer Engineering
Arts, Sciences and Engineering
Edmund A. Hajim School of Engineering and Applied Sciences

University of Rochester
Rochester, New York

2011
ii
Curriculum Vitae

The author was born in Hebei Province, China in 1980. He attended Nankai
University (Tianjin, China) from 1999 to 2006, and graduated with a Bachelor of
Science degree in Electronics in 2003 and a Master of Science degree in Optics in
2006. He came to the University of Rochester in the fall of 2006 and begun graduate
studies in the Department of Electrical and Computer Engineering with a
concentration in analog/radio-frequency integrated circuit design. He pursued his
research under the direction of Professor Zeljko Ignjatovic and received the Master of
Science degree from the University of Rochester in 2008.
iii
Acknowledgements
My graduate studies at the University of Rochester have been full of
opportunities to learn from a large body of faculty members and students with
extensive and profound knowledge. I would like to thank my advisor, Prof. Zeljko
Ignjatovic, for investing considerable time, effort and resources in my graduate
studies. He provided me invaluable guidance throughout the years and it is a privilege
to be in his group. I, also, want to thank the members of my thesis committee for
providing me insightful advice and feedback. Besides, I am grateful for the assistance
received from members of Prof. Ignjatovic's group, Prof. Mark Bocko's group and
Prof. Hui Wu's group, regarding computer environment setup, circuit design
discussion, testing assistance, and so on.
Thanks to the MOSIS Educational Program for the Sigma-Delta modulator
project fabrication in the IBM 130nm CMOS process.
iv
Abstract
We propose and verify the design of low-power, high-performance CMOS
Switched-Capacitor (SC) circuits for analog and radio-frequency (RF) applications. In
low-cost CMOS semiconductor processes, SC circuits play a crucial role in
implementing accurate analog signal processing functions. However, conventional SC
circuits are usually power-demanding due to the accurate signal settling requirement.
On the other hand, the shrinking of amplifier gain and voltage swing driven by
technology scaling makes SC circuit design in deep sub-micron CMOS processes
more and more challenging. To counteract these problems, low-power SC circuit
techniques suitable for deep sub-micron CMOS processes are investigated in this
work. In the first illustrative circuit example, a 2.5 GHz Phase-Locked-Loop (PLL)
employing a new low-power SC loop filter is proposed, designed and verified in a
0.18μm CMOS technology. By employing the proposed SC loop filter, the
advantages of low reference spur and small on-chip capacitor size are achieved.
While the loop filter consumes a very low power, 1/f noise introduced by the inverter
amplifier is also suppressed. The second circuit example is an audio-band
highly-linear low-power multi-bit Delta-Sigma (ΔΣ) modulator with a SC
nonlinearity-suppressed feedback DAC verified in a 0.13μm CMOS technology. By
employing this proposed scheme, problems with conventional methods to realize
multi-bit feedback DACs are circumvented. The power consumption of the proposed
method can be maintained low. A promising approach to implement practical
multi-bit ΔΣ analog-to-digital converters (ADCs) is demonstrated.
v
Table of Contents
Curriculum Viate ii
Acknowledgements iii
Abstract iv
List of Tables ix
List of Figures x
List of Acronyms xvii
Foreword 1
Chapter 1 Introduction 2
1.1 Motivation 2
1.2 Research Goals 3
1.3 Thesis Organization 6
Chapter 2 Switched-Capacitor Circuits 8
2.1 Discrete-Time Signal Basics 8
2.1.1 Spectra of Discrete-Time Signals 8
2.1.2 Sample-and-Hold Response 10
2.2 Building Blocks in Switched-Capacitor Circuits 11
2.2.1 Sampling Switches 11
2.2.2 Capacitors 16
2.2.3 Amplifiers 19
2.3 Noise in Switched-Capacitor Circuits 25
2.3.1 KTC noise 25
vi
2.3.2 Thermal noise of a switched-capacitor integrator 26
Chapter 3 PLL Frequency Synthesizer 31
3.1 PLL basics 31
3.1.1 Type I PLL 32
3.1.2 Type II PLL 35
3.2 PLL Building Blocks 44
3.2.1 Phase/frequency detector 44
3.2.2 Charge Pump 47
3.2.3 Programmable Divider 48
3.2.4 Voltage Controlled Oscillator 49
3.3 Implementation Issues and Noise 52
3.3.1 Implementation Issues 52
3.3.2 Noise Consideration at Different Nodes 55
Chapter 4 Delta-Sigma A/D Converters 58
4.1 A/D Conversion Basics 58
4.1.1 Sampling and Quantization 58
4.1.2 Oversampling ADC 61
4.2 Basics of Delta-Sigma ADCs 62
4.3 Higher-Order Delta-Sigma ADCs 67
4.3.1 Single-Loop ΔΣ modulators with Distributed
Feedback Paths 69
4.3.2 Single-Loop ΔΣ modulators with Feed-Forward Paths 72
vii
4.3.3 Stability of single loop ΔΣ modulators 75
4.3.4 MASH modulators 81
4.3.5 Techniques to enhance ΔΣ modulator performance 83
4.4 Thermal Noise in ΔΣ ADCs 86
Chapter 5 PLL Design with a Low-Power Active Switched-Capacitor Loop Filter
91
5.1 PLL Loop Filters in literatures 91
5.1.1 Active Continuous-Time Loop Filter 91
5.1.2 Passive Switched-Capacitor Loop Filter 93
5.1.3 Hybrid Loop Filter 96
5.2 Proposed Low-Power Active Switched-Capacitor Loop Filter 98
5.2.1 Sub-Threshold Inverter Amplifier 98
5.2.2 Design of the Low-Power Active Switched-Capacitor
Loop Filter 101
5.2.3 Reference Spur and Noise of the Loop Filter 109
5.3 Other Building Blocks of the PLL Prototype 112
5.3.1 Phase/Frequency Detector 112
5.3.2 VCO 113
5.3.3 Programmable Divider 117
5.4 Prototype Measurement Results 119
5.5 Chapter Conclusion 121
Chapter 6 A Multi-bit ΔΣ ADC with a Low-Power Switched-Capacitor
viii
Nonlinearity-Suppressed DAC 123
6.1 Existing Techniques to Enhance DAC Linearity 123
6.1.1 Layout considerations for capacitor matching 124
6.1.2 Calibration 126
6.1.3 Dynamic element matching 127
6.2 ΔΣ ADCs with Nonlinearity-Suppressed DACs 129
6.2.1 Switched-capacitor ratio-independent multiply-by-N 129
6.2.2 Low-power SC nonlinearity-suppressed DAC 139
6.2.2.1 Gain-Boosted Inverter Amplifier 139
6.2.2.2 Nonlinearity-suppressed DAC 142
6.2.2.3 Noise analysis for the
nonlinearity-suppressed DAC 149
6.2.2.4 ΔΣ ADC using the low-power
nonlinearity-suppressed DAC 159
6.3 Chip Measurement Results 160
6.4 Chapter Conclusion 164
Chapter 7 Conclusion 165
References 168
ix
List of Tables
Table Title Page
Table 3-1 Design parameters for a 2.4GHz PLL 53
Table 3-2 PLL Phase noise transfer function for different noise sources 56
Table 5-1 Karnaugh map for D1 119
Table 5-2 Karnaugh map for D2 119
Table 5-3 PLL performance comparison 122
Table 6-1 ΔΣ Performance summary and comparison 164
x
List of Figures
Figure Title Page
Figure 2-1 Sampling and Sample-and-Hold 9
Figure 2-2 Frequency domain illustration of sampling 10
Figure 2-3 Sample-and-Hold response 11
Figure 2-4 MOS sample-and-hold stage 12
Figure 2-5 Charge injection and clock feed-through suppression by
dummy switch 15
Figure 2-6 Cross section of a MIM capacitor 16
Figure 2-7 A charge redistribution DAC and its equivalent circuit during
output phase 17
Figure 2-8 A typical switched-capacitor integrator 20
Figure 2-9 Equivalent circuit of Figure 2-8 in Phase 2 22
Figure 2-10 Block diagram for a basic negative-feedback system 24
Figure 2-11 Bode plots of loop gain for a two-pole system 25
Figure 2-12 Sample-and-hold equivalent circuit during sampling phase 26
Figure 2-13 Input referred integrator thermal noise power versus g (R +R ) 28
m S1 S2
Figure 2-14 Opamp feedback circuit 29
Figure 2-15 Integrator noise model 30
Figure 3-1 Phase-locked loop block diagram 31
Figure 3-2 Magnitude and phase response of the Type I PLL loop gain 33
Figure 3-3 Second order Type II PLL block diagram 36