Channels LTE Filtering System Electrical and Computer Engineering

113 Pages·2013·1.81 MB·English

All Channels LTE Filtering System

Miguel Pereira Leite Fragoso

Thesis to obtain the Master of Science Degree in
Electrical and Computer Engineering

Examination Committee
Chairperson: Prof. João Manuel Torres Caldinhas Simões Vaz
Supervisor: Prof. José António Beltran Gerald
Member of the Committee: Profa Maria João Ramos Marques Coelho Carillho do
Rosário

October 2013
Acknowledgments

It is of my wholehearted will to say a big and grateful thank you to the following persons:
To my Family that always supported me.
To my Friends that were always there in the good times and in the bad times.
To my Supervisor, José Gerald, who always corrected my mistakes and taught me plenty. The
lessons learned will stay with me forever. His friendly, professional and dedicated character have truly
inspired me.
To Professor Horacio Neto for always being so kind and available with his help in making me
understand the mistakes I was making in the VHDL code of the FPGA simulation.

II
Abstract
4G is the fourth and most recent generation of mobile communications standards; LTE (Long Term
Evolution), marketed as 4G LTE, is a standard for high-speed data mobile phones and data terminals.
It uses scalable channel bandwidths of 5 to 20 MHz (optionally up to 40 MHz).
Governments of many European countries (as for instance, Portugal) are releasing (licensing)
these LTE bands to private Institutions. The exhaustive use of this spectrum makes it difficult to avoid
interference from adjacent channels, limiting the signal data rate. Very selective channel filtering is
thus mandatory and suitable filters have to be developed for that purpose.
One of these LTE (TDD) channels is the LTE band 38 occupying from 2570 to 2620 MHz.
A goal to be reached, suggested by a Portuguese mobile phone company, is to design a filter with
central frequency 2585 MHz and 20 MHz of bandwidth achieving 80 dB attenuation at 5 MHz beyond
each side of the band. This kind of very selective filter does not exist in the market today. To note that
this filter was supposed to be applied to LTE band 38.
A functional filter architecture with the previous mentioned filtering properties and suitable for being
used in almost any LTE band (not only in band 38) is proposed in this thesis. The filtering system’s
behavior is fully simulated using MATLAB and the FPGA block using ISE.

Keywords: All channels, LTE Filter, Downconversion, FPGA, Upconversion, Simulations.

III
Resumo
4G é a quarta e mais recente geração de normas de comunicações móveis; LTE (Long Term
Evolution) comercializado como 4G LTE é uma norma de dados de alta velocidade para telefones
móveis e terminais de dados. Esta utiliza canais escaláveis com largura de banda entre 5 e 20 MHz
(opcionalmente pode subir até 40 MHz).
Governos de muitos países Europeus (como por exemplo Portugal) estão a libertar (licensiar) estas
bandas LTE para instituições privadas. O uso exaustivo do espectro torna difícil evitar a interferência
de canais adjacentes, limitando a velocidade de transferência de dados do sinal. Uma filtragem muito
selectiva de canais é então obrigatória e filtros adequados necessitam de ser desenvolvidos para
esse propósito.
Um desses canais LTE (TDD) é a banda LTE 38 que ocupa desde 2470 a 2620 MHz.
Um objectivo a ser alcançado, sugerido por uma empresa de comunicações móveis Portuguesa, é
desenhar um filtro com frequência central 2585 MHz e 20MHz de largura de banda, que alcance 80
dB de atenuação em apenas 5 MHz para além de cada um dos lados da banda. Este tipo de filtro,
muito selectivo, não existe no mercado actualmente. Note-se que é aplicar este filtro à banda LTE 38.
Uma arquitectura funcional do filtro com as propriedades previamente mencionadas e além disso
adequada para ser usada na grande maioria das bandas LTE (e não apenas na banda 38) é proposta
nesta tese.

Palavras Chave:
Filtro LTE, Qualquer Canal, Downconversion, FPGA, Upconversion,
Simulações.

IV
Contents
Acknowledgments ...............................................................................................................................II
Abstract .............................................................................................................................................III
Resumo ............................................................................................................................................ IV
List of Figures .................................................................................................................................. VII
List of Tables .................................................................................................................................... XI
Acronyms List ................................................................................................................................. XIII
1. Introduction ............................................................................................................................. XIV
1.1 Introduction ........................................................................................................................... XIV
1.2 Filter Specifications ............................................................................................................... XIV
1.3 LTE Bands ............................................................................................................................. XV
1.3.1 Band 1 ............................................................................................................................. XV
1.3.2 Band 2 ............................................................................................................................. XV
1.3.3 Band 3 ............................................................................................................................. XV
1.3.4 Non Supported Band ....................................................................................................... XV
1.4 General Architecture .............................................................................................................. XV
1.5 Dissertation Outline ............................................................................................................... XVI
2. Downconversion ........................................................................................................................ XVII
2.1 Introduction .......................................................................................................................... XVII
2.2 Downconversion Block (Block A) ......................................................................................... XVIII
2.3 Downconversion Block SNR ................................................................................................... XX
2.3.1 Downconversion Block initial SNR ................................................................................... XX
2.3.2 Downconversion Block SNR Degradation ....................................................................... XXI
2.4 Mixers .................................................................................................................................XXIV
2.4.2 Up mixing and Down Mixing..........................................................................................XXIV
2.4.3 Mixing modes and concepts...........................................................................................XXV
2.4.5 Noise Figure ............................................................................................................... XXVIII
2.4.6 Downconversion Mixer Selection ..................................................................................XXIX
2.5 Down Conversion Process ...................................................................................................XXX
2.5.1 First Step .......................................................................................................................XXX
2.5.2 Second Step .............................................................................................................. XXXVI
2.5.3 Pre-Processing Before the Analog to Digital Conversion ........................................... XXXVII
2.5.4 Simulated range of the Attenuation filters in the Down conversion Block .......................... XL
3. FPGA Block ............................................................................................................................... XLII
3.1 Introduction .......................................................................................................................... XLII
3.2 ADC ..................................................................................................................................... XLII
3.2 Digital Filter .................................................................................................................... XLV
V
3.2.1 Digital Filter Higher Level Design for the FPGA .............................................................. XLV
3.2.2 Digital Filter Lower Level Design for the FPGA ............................................................ XLVIII
3.3 Equalizer ....................................................................................................................... XLIX
3.4 DAC .........................................................................................................................................LI
4. Upconversion ................................................................................................................................ LII
4.1 Introduction ............................................................................................................................. LII
4.2 Upconversion Block (Block B) ........................................................................................... LIII
4.3 Upconversion Block SNR ....................................................................................................... LV
4.4 Up Conversion Process .................................................................................................. LVII
4.4.1 First Step ....................................................................................................................... LVII
4.4.2 Second Step ................................................................................................................ LVIII
5. Matlab and FPGA Simulations ................................................................................................. LXVIII
5.1 Single Run Matlab Simulation ............................................................................................ LXVIII
5.1.1 OFDM Signal generation ............................................................................................ LXVIII
5.1.2 Analog Filters Simulation .............................................................................................. LXIX
5.1.3 Matlab Simulation Results ............................................................................................ LXIX
5.2 FPGA Simulation ............................................................................................................. LXXXV
5.3 Multiple Run Matlab Simulation ...................................................................................... LXXXVI
6. Final Remarks .................................................................................................................... LXXXVIII
6.1 Future Work ................................................................................................................. LXXXVIII
6.2 Conclusions ................................................................................................................... LXXXIX
7. References .................................................................................................................................. XC
Appendix ...................................................................................................................................... XCIII
1.1 LTE Bands details ............................................................................................................... XCIII
2.1 Algorithm for SNR Degradation determination ..................................................................... XCV
2.2 Single MosFET Mixer Analysis ........................................................................................... XCVI
2.3 Tables of functional filters’ components ............................................................................ XCVIII
2.5 Filter conversion to Microstrip line technology ......................................................................... CII
3.1 ADC - Some important specifications ..................................................................................... CIV
3.2 ADC – Types of Error ............................................................................................................. CV
3.4 Study of IIR filters as the FPGA Digital Filter .................................................................. CVIII
3.5 Detailed Information of FIRs’ hardware implementation .................................................. CVIII
5.1 Recursive Calculations For Filters’ Frequency Response Matlab Simulation .......................... CIX
5.2 IP3 Error after each mixing step............................................................................................ CXII

VI
Pages
List of Figures
Figure 1.1 – Ideal LTE filter specifications……………………………………………………………………………...XIV
Figure 1.2 – Filtering system’s general architecture. ………………………………………………………………….XVI

Figure 2.1 – Used architecture for block A……………………………………………………………………………XVII

Figure 2.2 – Scheme that exhibits the operation of block A1………………………………………………………..XVIII

Figure 2.3 – A simple scheme of a downconversion mixer………………………………………………………….XXIV

Figure 2.4 – A simple scheme of an upconversion mixer……………………………………………………………XXIV

Figure 2.5 – Operation of an ideal downconversion mixer for a single frequency signal. ……………………….XXIV

Figure 2.6 – Operation of an ideal upconversion mixer for a single frequency signal…………………………….XXV

Figure 2.7 – Schematic of a simple and representative continuous non-linear mode mixer……………………...XXV

Figure 2.8 – Graphical determination of the third order intercept point……………………………………………XXVII

Figure 2.9 – Ring mixer waveforms…………………………………………………………………………………..XXVIII

Figure 2.10 – Noise generated by a downconversion image band in the frequency domain……………………XXIX

Figure 2.11 – Schema of the downconversion of the signal to 600 MHz…………………………………..............XXX

Figure 2.12 – Illustration of band 1 and the matching dynamic range of the LO frequency……………………...XXXI

Figure 2.13 – Highest frequency image band and LTE lower frequency band in band 1. …………………….XXXII

Figure 2.14 – HP Filter Specifications to Reject the Image Band of Band 1……………………………..............XXXII

Figure 2.15 – HP Filter Circuit to Reject the Image Band of Band 1……………………………………...............XXXII

Figure 2.16 – Illustration of band 2 and the matching dynamic range of the LO frequency…………………….XXXIII

Figure 2.17 – Highest frequency image band and respective LTE band in Band 2……………………………..XXXIII

Figure 2.18 – HP Filter Specifications to Reject the Image Band of Band 2……………………………………..XXXIV

Figure 2.19 – HP Filter Circuit to Reject the Image Band of Band 2……………………………………………...XXXIV

Figure 2.20 – Illustration of band 3 and the matching dynamic range of the LO frequency. …………………..XXXIV

Figure 2.21 – Highest frequency image band and respective LTE band in Band 3. …………………………….XXXV

Figure 2.22 – High Pass Filter Specifications to Reject the Image Band of Band 3……………………………..XXXV

Figure 2.23 – HP Filter Circuit to Reject the Image Band of Band 3……………………………………………...XXXVI

Figure 2.24 – Schema of the downconversion from 600MHz to a 60MHz……………………………………….XXXVI

Figure 2.25 – HP filter Specifications to Reject the Image Band before 2nd downconversion step…..............XXXVI

Figure 2.26 – HP Filter Circuit to Reject the Image Band before 2nd dowconversion step…………………...XXXVII

VII
Figure 2.27 – Schema of the replica generation of the signal digitalization process…………………………...XXXVII

Figure 2.28 – Digitalizing a band pass signal in 60MHz with an (cid:1858) of 250 MSPS…………………….............XXXVIII
(cid:3046)

Figure 2.29 – Adjacent Replicas interference in digitalizing the band pass signal. ………………………......XXXVIII

Figure 2.30 – Band pass filter for cleaning the signal spectrum of the input of the ADC……………………..XXXVIII

Figure 2.31 – Low pass filter to attenuate the LO tone inserted in the second mixing step………………………...XL

Figure 3.1 – Internal constitution of the FPGA block…………………………………………………………………..XLII

Figure 3.2 – Magnitude response of Equiripple solution with (cid:1827) =1 (cid:1856)(cid:1828)……………………………………..........XLVI
(cid:3043)

Figure 3.3 – Simplified example of a systolic parallel FIR implementation. ……………………………………...XLVIII

Figure 3.4 – Simplified example of a symmetric systolic parallel FIR implementation…………………………....XLIX

Figure 3.5 – Frequency response of the FIR equalizer designed……………………………………………………….L

Figure 4.1 – Architecture to be used to construct block B. …………………………………………………………….LIII

Figure 4.2 – Scheme that exhibits the operation of block B1………………………………………………………….LIV

Figure 4.3 – Schema of the upconversion of 60MHz to 600MHz……………………………………………............LVII

Figure 4.4 – Response of Band Rejection Filter to attenuate 540 MHz LO leaked tone . ………………...........LVIII

Figure 4.5 - BR Filter Circuit to attenuate the LO leaked tone in 540 MHz. ………………………………………LVIII

Figure 4.6 – Schema of of upconversion from 600 MHz to LTE band chosen……………………………………...LIX

Figure 4.7 – Response of HP Filter to reject the variable LO leaked tone in Band 1………………………………LXII

Figure 4.8 – HP Filter Circuit to Reject the Variable LO leaked tone in Band 1…………………………………….LXII

Figure 4.9 – Response of HP Filter to reject the LO leaked tone in Band 2 Sub Band 1………………………….LXII

Figure 4.10 – HP Filter to reject the LO tone in in Band 2 Sub Band 1………………………………..……………LXIII

Figure 4.11 – Response of HP Filter to reject the LO leaked tone in Band 2 Sub Band 2………………............LXIII

Figure 4.12 – HP Filter to reject the LO leaked tone in Band 2 Sub Band 2……………………………………….LXIII

Figure 4.13 – Response of HP Filter to reject the LO leaked tone in Band 2 Sub Band 3……………………….LXIV

Figure 4.14 – HP Filter to reject the LO leaked tone in Band 2 Sub Band 3………………………………...........LXIV

Figure 4.15 – Response of HP Filter to reject the LO leaked tone in Band 3 Sub Band 1………………………..LXV

Figure 4.16 – HP Filter to reject the LO leaked tone in Band 3 Sub Band 1………………………………………..LXV

Figure 4.17 – Response of HP Filter to reject the LO leaked tone in Band 3 Sub Band 2……………………......LXV

Figure 4.18 – HP Filter to reject the LO leaked tone in Band 3 Sub Band 2……………………………………….LXVI

Figure 5.1 – Scheme of the generation of an ofdm signal centered at frequency (cid:1858)…………………………….LXVIII
(cid:3030)

Figure 5.2 – Power spectrum at the entrance of block A……………………………………………………............LXX

Figure 5.3 – Zoom in of power spectrum of signal at the entrance of block A………………………...................LXX

Figure 5.4 – Power spectrum after HP Band 3………………………………………………………………………..LXXI
VIII
Figure 5.5 – Zoom in of power spectrum of the signal after HP Band 3…………………………………………..LXXI

Figure 5.6 – Power spectrum after the Down Conversion first mixing step……………………………………….LXXII

Figure 5.7 – Power spectrum of the LO Isolation error………………………………………………………...........LXXII

Figure 5.8 – Zoom in of power spectrum of signal after DC 1st mixing step……………………………….........LXXIII

Figure 5.9 – Power spectrum after second Image band Rejection Filter………………………………………….LXXIII

Figure 5.10 – Zoom in of power spectrum of signal after FRI2…………………………………………………….LXXIV

Figure 5.11 - Power spectrum after the Down Conversion second mixing step…………………………………LXXIV

Figure 5.12 – Zoom in of power spectrum of signal after DC 2nd mixing step………………………….………LXXV

Figure 5.13 - Power spectrum after the Pre Processing Band Pass Filter………………………………………..LXXV

Figure 5.14 – Zoom in of power spectrum of signal after the Band Pass Filter. ……………………………….LXXVI

Figure 5.15 - Power spectrum after the Pre Processing Low Pass Filter…………………………………………LXXVI

Figure 5.16 – Zoom in of power spectrum of signal after the Low Pass Filter………………………................LXVII

Figure 5.17 - Power spectrum after the Analog to Digital Converter………………………………………............LXVII

Figure 5.18 - Power spectrum after Normalization before the FPGA Digital Filter………………………………LXVIII

Figure 5.19 - Power spectrum after FPGA Digital Filter, after Renormalization. ………………………………..LXVIII

Figure 5.20 - Power spectrum after FPGA Equalizer and power adaptation for 1st UC mixer………………….LXXIX

Figure 5.21 - Power spectrum after Oversampling..…………………………………………………………………LXXX

Figure 5.22 - Power spectrum after the Sample and Hold………………………………………………………….LXXX

Figure 5.23 - Power spectrum after the DAC ideal Low Pass Filter………………………………………………..LXXX

Figure 5.24 - Power spectrum after first Upconversion mixing step. ……………………………………………..LXXXI

Figure 5.25 - Power spectrum after Upconversion first Image Band Rejection Filter. ………………………….LXXXI

Figure 5.26 – Filter response of BR Filter, that functions as Notch at 540 MHz………………………………...LXXXII

Figure 5.27 - Power spectrum after “Notch” at 540 MHz…………………………………………………….........LXXXII

Figure 5.28 - Power spectrum after the Upconversion second mixing step……………………………….......LXXXIII

Figure 5.29 – Zoom in of power spectrum of the signal at IF and of its respective image band……………...LXXXIII

Figure 5.30 - Power spectrum after HP Band 3……………………………………………………………………LXXXIV

Figure 5.31 - Power spectrum after HP filter structure to reject the variable LO tone (block B1)………........LXXXIV

Figure 5.32 – Zoom in of power spectrum of signal after block B1…………………………………...………….LXXXV

Figure 5.33 – Comparison between FPGA simulated in ISE and simulated in MATLAB..……………………LXXXVI

Figure 5.34 - Power spectrum at end of LTE filter, Montecarlo Simulation of 15 sequential runs…………..LXXXVII

Figure 5.35 – Zoom in of power spectrum of Montecarlo Simulation. See ripple and SNR………………….LXXXVII
IX
Figure a2.1 – First equivalent circuit with ideal transmission lines of the LP filter…………………………………...CII

Figure a2.2 – Kuroda identities. Case a)………………………………………………………………………………...CIII

Figure a2.3 – Kuroda identities. Case b)……………………………………………………………………………......CIII

Figure a2.4 – Transmission line filter schematic after insertion of 2 unit elements………………………...............CIII

Figure a2.5 – Transmission line filter schematic after application of the Kuroda identities……………………….CIV

Figure a3.1 – Graphical representation of the SFDR in dBc and dBFS……………………………………………..CV

Figure a3.2 – Representation of a generic and ideal DAC transfer function…………………………………………CV

Figure a3.3 – Representation of an ideal 3 bit DAC transfer function………………………………………………...CV

Figure a3.4 – ADC offset error graphical example……………………………………………………………………..CVI

Figure a3.5 – ADC gain error graphical example. ……………………………………………………………………..CVI

Figure a3.6 – ADC DNL error graphical example………………………………………………………….................CVII

Figure a3.7 – ADC INL error graphical example..……………………………………………………………………..CVII

Figure a3.8 – Simplified serial FIR implementation………………………………………………………….............CVIII

Figure a3.9 – Example of a transposed parallel FIR implementation………………………………………………..CIX

Figure a5.1 – Ilustration of a generic lumped component filter of even order……………………………………….CIX

Figure a5.2 – General representation of a lumped component filter of odd order…………………………………..CX

Figure a5.3 – Capacitor and respective impedance…………………………………………………………………..CXI

Figure a5.4 – Inductor and respective impedance……………………………………………………………………CXI

Figure a5.5 – Inductor and capcitor in parallel and respective impedance…………………………………………CXI

Figure a5.6 – Inductor and capcitor in series and respective impedance…………………………………………..CXI
Figure a5.7 – IP3 error after first downconversion mixer……………………………………………………………..CXII

Figure a5.8 – IP3 error after second downconversion mixer…………………………………………………………CXII

Figure a5.9 – IP3 error after first upconversion mixer………………………………………………………………..CXIII

Figure a5.10 – IP3 error after second upconversion mixer. ………………………………………………………...CXIII

X