Table Of ContentContents, February 1981
J. F Relaae Compiling Throo-Adrase Cade for € Programs
J Cannitt -ADiatal Cancentistor or the SLO™86 System
Shaving in 1O-Ge
Moseting Muitpath Fading Resborwex Using Mul-
{one Prebing Snnal and Polym Aopronination
‘ih Quality Mesauroment Plan
2.0. Gitinand Fractonlly Spaced Equnizmon: An imeroved Digit
8.8 Weinstan ‘ronevoreal Equalizer
_
Re 1TheSi asec cunt cenigwain Moe 2
DIGITAL CONCENTRATOR FOR SLC-6 SYSTEM 129
or heavy lonling or mandatory monitoring purposes sk tafe
sedministration aids are provider
(2). A two-digie numeric display in provided on the faeplate of the
‘Cor Tat which display, upon demand, the peak traffic hurwred all
‘seconds perhour (608), per concentrated Gimeslot since the internal
‘rffic roster wns Tat cloned. The register is cleared by means of
pin jack othe Faceplate.
(Wd) The same daplay wil aleo indicate the mumber of blocked eal
up to a maximum of 15, sinoe the inlarnl blocked calls register was
last cleared. This roster is cleared by means of the pin jack.
{ui A traffic lamp is provided onthe faceplate, in conjunction with
‘aminor alarm, that indians here has boon two oe more block calls
for two out of three weeks running, This alan must be manually
seared through th pin jac
{iv} A relay closure is provided to remote to an electronic ewitching
system (ess) office that all T1 time slots are in uso. "The office can
then divert terminating calls an provide tc uwn eoorder tone while
keeping individual Tine Mockaye slatsioe (Tn noncesa Central OMice
this diversion will nol vecur and Ube tau will provide a digital reorder
tore}
[e} Asecond rey is provided that ourpulees peak weekly cai in
‘8, once por weok, toa rote trffic monitoring register atthe rate
fat one pulke per second
(i) A thied relay is provided that outpulaea the number of blocked
‘alle ge they occur to a remota blocked eals monitoring rier atthe
rate of 1 pulse per second, ‘There i na aaluration lit here as there
‘eas in the faceplate csp.
{n. TAU FUNCTIONAL DESCRIPTION
‘The following definitions are given to clarify all discussion that
Fallows: A Tne refers to a subscriber loop at the ac of a wie pair
‘appearance at the ovr. A channel unit ie the physical plugin serving
‘eof tw ines end providing the per-line crew fnetions A channel
fs the electrical path roma channel unit to the Transat Receive Uni
(anu) serving ity and the time alot renerved forthe Tine nto and out of
the mm on the 1-544 megahe serial pew busses, Channels ener or
leave the eoncentnitor ne Limi lls from orto the rar. Time slots om
the TI line interfacing wo the concentrator ae referred to aa trunks,
‘because they provide a limited number of shared path betreen the
wo terminals of the system, in analogy with traditional crunking
facilites betwen contra ofc
3.4 System Dock aaaram
Figure 2 shows a simplified aystom block diggram of the tats. The
microcomputer controllers are realized using the Ball Laborstories
4124 THE BELL SYSTEM TECHNICAL JOURNAL, FEBRUARY 1861
Vi 2s prem ee gam,
designe MAC-# microprocestor” The MAC-8 microcomputers main
tain contzol over (ho Tirwe Slot Inerehange (151) chips abd talk
tach erher over a datalink channel derived from the mbtrome bite on
the Tine, The tranemil181 wlecively combines two 1544 megabi,
Serial vot bie stream, one from each of the rau it sorves. (A TRO
performs the A/D, D/A, unl eating tasks for 24 channels) The
eulting TL signals snl to che seoeive 13 atthe olber ed of the
syotem where i + expanded into feo stcams, for sending lv enrre
ponding ies, The Tee provide fll accom, ming that any ane of
the invonsing (outgoing) 48 lines or line slo has accena to any one of
vB enlgoing {incoming} Irani, where true are ine alts on the
Tl line. The cor TAD halos trunk assignmente and, in goneral,
Control the concenimtor, The kx TAU aete more an xnav. When the
MACS controller wna line fo a specifi tank, tac line wll keep
the trunk forthe duration of he ell ml no say inbibite any of the
folher lines rom accessing any of he ther ims
‘A lineservice requer, called “ati,” ia piled up bythe trait
vet by assessing thy A od F.bit eignaling bussos on the xysiem
hheckplane. ‘und sare che tandord nomenclature fur perchannel
inating that indicate of-hooe, rng, ol "The activi i scored in
Iemory in Uhe tay fin which ie cat be reteieved by che MACS
through the Ts mivroremputar address and data ports. Activity at che
Tat is passed over the dava link In the cow where the lne/trunke
osiamints are decermined
DIGITAL CONCENTRATOR FOR SLO-96 SYSTEM 125
“The tripe and receive 3504 must be wynehronizad We the TRUS
they serve ancl uphimoprine signals see provided for Unie pose, No
synehroniaaton is argumed between transmit and 2ecsive Tain FUR.
ther, no aymchrenization is assumed berween the MAC-S, thesia, and
the data link. The sts are acceatod by moans ofa handshake proc
tae, The dec-link frame signals are poled to determine when mee
ange processing is needed.
‘all 24 trunks are buy, provision is needed for feeding a fast-buay
(overfom) tone to the co¥ channel units hia a done digitally through
tho receive 0, rosltng in significa. cost savings in ebo channel
‘units. The reeeve rt allows the assignment of up to 24 Tine to “bus
‘ane? hereby the sleccad nen necsive a fast-hary tone in pow
form aa read from a codo-word tablo stored in the MAC-# program
memory. Signaling information (A and Fei i abe sored in thous
Codes und Uherby allows the chriel wal to erie hat i ene
tho fast-busy tone und uecordingly tsp ringing without charge, prior
oupplying the ton on the Dlorkel eastaner ine,
1.2 Giri block eagram
igure 3 show a simplified schematic forthe cow 4c. The er TAU
ia nearly identical wich the basic exceptions that Outguc Port 2 is
removed and there i na Thead Only Memory 2 (nose). ‘The Random
‘Rereat Memory (R43), Read Only Memory (now), Thput Per, al
‘Outont Ports connect to the MACHA hun atin any normal eer
pter.'The enstomn Ta chipe were also dasigned ca conmece direct on
the bot a appear to the MACS as programmable peripheral chips,
‘The MACE lath lo thee chips by meane af handshake proceine
using the MAC-8 Daca Ready line, The elock frequency for the Ts
land MAC-A is 1.64 MHz, Thee to nine wait mates rule, as required
land generaced by the 1si on a read ur write, The rai chip generates
land responds to the necessary signals for system synchronization
‘Output Port 1 provides four alarm lighe emitting diodes (une) an
the faceplate and three aystem alarms. For the cor rau, the Leos
indicate alarms for cor, wr, trafic, and special-service channels. The
zr Tau has only two Lube indicating uv alarm and unit alarm for
speciaeavice chun, The system alarms are minor, man, At
‘ajo with channel uni elisa, Outpt Port 1 sso proves wm opt
for suobing the sanity mowmlable, Laeout deview hal checks on
proper sequencing of the progeam. Output Port 2 provides dhe dal
Sixt aumeric display for indenting traffc anal blacked calls on the
facoplate and also services the three relays used for remoting concen
{tor status, The Tnpat Port peewides forthe display selection switehes
sand the iternalreister-clening pin jack, ll mounted on Che faeeptnte
Tefarther provides inputs for the data-ink frame signal which are
polled to determine datating message requests. Also the Input Pore
allows accessing « reeeiver out-of frime signal nnd bank Taop-back
signal
The oon TaD has 4K bytes of program meinory an the RE Tat has
2K bytes. Bach are realized using 2K byte RoM chips. At both co7 and,
ier 1K bytes of RAM are provided, thongh the co7 uses Tess than ene
thine! af the weilnhla memory and dhe 7 woes only about one-fourth
‘The Tau plug-ins are printed civuit cards measuring approximately 4
finches by 10 nebox plan in Pig. Tens required Una the PAU
sited tn physically ype the Line Lncertace Unica fe the Tne
that are not needed in the concentrated mode. Power supplies forthe
‘rau are 5V and 12V, with typicel dissipation being about 3 watts
Special requirements ad to bo met for tho 1 raU oo that i could
work ever the Lemperature range af to +45 dogs Celso
IV. HARDWARE AND SOFTWARE FEATURES
4:1 Features ofthe TSE
‘The rat chip was designed to be universl, in the sense that itis
package lead and microcomputer programmable for use at COT ot,
for either the transmit or reer function. In king w univers ebip
‘nth al the fesborss mentions below i. ix posible, and very descabe,
to reuse pioots of the hardware inside the chip, Thus, for example,
Ploces of nam and athe harware used for busy trunk nsignmente
the revise ra mele are aliemnatively ued in the ral T mde
for the activity and “exe” collection (izcusced later). Simiaely,
‘many input and output package leeds ferve dval purposes. Tn ain
to che hac feazures,ceveral very important additional faturea see
Pig ou cee pack
provided by the 181 chip, Most of ehese features cost very Title
Reardvare, that is, they inezeore chip complenity very litle, while
providing weful features
Figure 8 isa block diagram of the 181 chip. The heart ofthe chip is
‘nab used for Pom data trunk assignment information, busy trunk
ftesignment information nliily data, "INN" data, pertne es bits,
T byte of fasvchury tone buler, and 2 bytos of ROM, Incoming and
‘outgoing serial Pom data it handled in bytos inside the chip by feeding
he'daca through sorl-to-jorallel ragivne (Registers 1 and 2) and
Dralleto-enal registers (Registars 2 and 9). The use of Register 2
‘ependa on whether the Tati performing in the transmit or receive
inode, The frame bit is normally stored inthe vi wv (ame Bip op),
‘The main ence lagi provides the siguala for concraling all the chip's
registers multiplexer and mast Multiplesers we include or selecting
Iidress and data for the Raat and for selecting output onto the
‘microcomputer data but
4.1.1 Intechangig tne sors
‘Te time-slot interchange is executed by the method of writing dats
into a kao vequentally and reading it selectively for the transmit
Concentrator function and viee versa for the reoeive fonction. "The
funk assignments (24 bytee), which are addveaes of che desired Poo
Tine daca, are stored in the nam, Yat are used to addres’ the mast
128 TWEGELL SYSTEM TECHNICAL JOURNAL. FEBRUARY 1981
selectively by a feedback register (Register 4) ro the address bu Fach
‘ofthe trunk (bury trunk) assignments are fed back in ten to addres
‘the decir ine memory. In the transmit mode, ifs trunk is unassigned,
the Hom locations aze acensed ( send idle cole on the Tne. Ia the
receive mode, ia line is unassigned, idle code from the Pes memory
‘sread out for the line or idle is forced by means ofa cleared “enable
Ti liscussed late.
ince the concentrator is positioned between the 7RUe and the TL
in, A and B bit signaling information is already contained in he Few
bitntesina when they are received by the ra Itianecestary, therefore,
(hat the 181 insure integrity of whaling frames. Signaling frames are
the 6th and 17th frames ofa 12-rame sequence and contain the per-
Shannel A and B bit agnaling information inthe leat significant bit
of the re code words. Integrity is mainteined by having two Axe
fection of rea data (48 bytes each). While writing (reading) in one
‘Section cequentially, the other ection is ond (mitten) selectively: the
voles are severeed every frame. ‘The frame bit is comespondingly
eleved to match up with the outgoing doce. "The results that
iznnling-rame intogrity it maintained while the data experiences
fixed delay of approximately Gwo Trames (250 microseconds) end-to-
rb regal of the Tine or tr
The microcomputer has access to the Ts1 memory through the
saddrese and date ports of tho Ts chip (se Fig 5). "This llowe all the
‘memory locations. including the rom data memory, to be watten and
read. ‘The main control block ofthe TStcontaine a frame counter for
‘anteaing all chi sequencing. When the counter in slate mot
heed for a apecifc internal fanetin, that lock eyeles can be used to
respond to a microcomputer read or write requeet. ‘The result
variable number of wait stats, us mentioned earlier, because the
‘microprocessor can request a TST aceess at an arbitrary time. ‘The
Inicrocompter talks tn the rst by tneans of Read/Write, Select, wna
By Teds thal connect to the micencompater interfae circutzy, On
«reel operation the dala it eld in Register 6 a0 chat the processor
on nse a mach Lime a8 neacanry to recognize the da, Some ofthe
Indien apace of the rai reseved for addressing he datatnk rior
(Register 7) ond actviy-mmode contol register (Register 8)
4.8 System synchronization
"Theta must be synchronize tothe nats to knove whoro ovory bit
in the incoming and outgoing bitstreams i located. For the transmit
Function, the Ter puls oul & sperrame synechroaiattion signal which
‘the snus can accept and lock to, For the receive function the 731
190. THE BELL SYSTEM TECHNICAL JOURNAL, FEBRUARY 1981
