Table Of Content

Assembly Language Programming Assembly Language Programming ARM Cortex-M3 Vincent Mahout Firstpublished2012inGreatBritainandtheUnitedStatesbyISTELtdandJohnWiley&Sons,Inc. Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permittedundertheCopyright,DesignsandPatentsAct1988,thispublicationmayonlybereproduced, storedortransmitted,inanyformorbyanymeans,withthepriorpermissioninwritingofthepublishers, or in the case of reprographic reproduction in accordance with the terms and licenses issued by the CLA. Enquiries concerning reproduction outside these terms should be sent to the publishers at the undermentionedaddress: ISTELtd JohnWiley&Sons,Inc. 27-37StGeorge’sRoad 111RiverStreet LondonSW194EU Hoboken,NJ07030 UK USA www.iste.co.uk www.wiley.com ©ISTELtd2012 TherightsofVincentMahouttobeidentifiedastheauthorofthisworkhavebeenassertedbyhimin accordancewiththeCopyright,DesignsandPatentsAct1988. ____________________________________________________________________________________ LibraryofCongressCataloging-in-PublicationData Mahout,Vincent. Assemblylanguageprogramming:ARMCortex-M3/VincentMahout. p.cm. Includesbibliographicalreferencesandindex. ISBN978-1-84821-329-6 1. Embeddedcomputersystems.2. Microprocessors.3. Assemblerlanguage(Computerprogram language) I.Title. TK7895.E42M342012 005.2--dc23 2011049418 BritishLibraryCataloguing-in-PublicationData ACIPrecordforthisbookisavailablefromtheBritishLibrary ISBN:978-1-84821-329-6 PrintedandboundinGreatBritainbyCPIGroup(UK)Ltd.,Croydon,SurreyCR04YY Table of Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix Chapter1.OverviewofCortex-M3Architecture . . . . . . . . . . . . . . . . 1 1.1.Assemblylanguageversustheassembler . . . . . . . . . . . . . . . . . . 1 1.2.TheworldofARM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2.1.Cortex-M3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2.2.TheCortex-M3coreinSTM32. . . . . . . . . . . . . . . . . . . . . . 7 Chapter2.TheCoreofCortex-M3 . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.Modes,privilegesandstates. . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.1.RegistersR0toR12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.2.TheR13register,alsoknownasSP. . . . . . . . . . . . . . . . . . . 19 2.2.3.TheR14register,alsoknownasLR. . . . . . . . . . . . . . . . . . . 20 2.2.4.TheR15orPCregister. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.5.ThexPSRregister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Chapter3.TheProperUseofAssemblyDirectives . . . . . . . . . . . . . . . 25 3.1.Theconceptofthedirective . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.1.Typographicconventionsanduseofsymbols . . . . . . . . . . . . . 26 3.2.Structureofaprogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.1.TheAREAsections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.Asectionofcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.1.Labels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.2.Mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.3.3.Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3.4.Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.3.5.Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 vi AssemblyLanguageProgramming 3.4.Thedatasection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.4.1.Simplereservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.4.2.Reservationwithinitialization . . . . . . . . . . . . . . . . . . . . . . 37 3.4.3.Datainitialization:thedevilisinthedetails . . . . . . . . . . . . . . 39 3.5.Isthatall?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.5.1.Memorymanagementdirectives. . . . . . . . . . . . . . . . . . . . . 40 3.5.2.Projectmanagementdirectives. . . . . . . . . . . . . . . . . . . . . . 41 3.5.3.Variousandvarieddirectives. . . . . . . . . . . . . . . . . . . . . . . 44 Chapter4.OperandsofInstructions . . . . . . . . . . . . . . . . . . . . . . . . 47 4.1.Theconstantandrenaming. . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.2.Operandsforcommoninstructions. . . . . . . . . . . . . . . . . . . . . . 49 4.2.1.Useofregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.2.2.Theimmediateoperand . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.3.Memoryaccessoperands:addressingmodes . . . . . . . . . . . . . . . . 57 4.3.1.Thepointerconcept . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.3.2.Addressingmodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Chapter5.InstructionSet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.1.Readingguide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.1.1.Listofpossible“condition”suffixes. . . . . . . . . . . . . . . . . . . 65 5.2.Arithmeticinstructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.3.Logicalandbitmanipulationinstructions. . . . . . . . . . . . . . . . . . 70 5.4.Internaltransferinstructions. . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.5.Testinstructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.6.Branchinstructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.7.Load/storeinstructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.7.1.Simpletransfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.7.2.Multipletransfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.7.3.Accesstothesystemstack . . . . . . . . . . . . . . . . . . . . . . . . 84 5.8.“System”instructionsandothers . . . . . . . . . . . . . . . . . . . . . . . 85 Chapter6.AlgorithmicandDataStructures . . . . . . . . . . . . . . . . . . . 87 6.1.Flowchartversusalgorithm . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.2.Alternativestructures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.2.1.Simple(orshortened)alternative. . . . . . . . . . . . . . . . . . . . . 89 6.2.2.Completealternative. . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.2.3.Specialcaseofthealternative . . . . . . . . . . . . . . . . . . . . . . 93 6.2.4.Multiplechoice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.3.Iterativestructures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.3.1.TheRepeat…Untilloop . . . . . . . . . . . . . . . . . . . . . . . . . . 98 TableofContents vii 6.3.2.TheWhile…Doloop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.3.3.TheFor…loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.4.Compoundconditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.4.1.AlternativewithAND . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.4.2.IterationwithAND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.4.3.AlternativewithOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.4.4.IterationwithOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.5.Datastructure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.5.1.Tableinonedimension . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.5.2.Tablesinmultipledimensions . . . . . . . . . . . . . . . . . . . . . . 112 6.5.3.Registration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.5.4.Non-dimensionaltable,characterstring. . . . . . . . . . . . . . . . . 113 6.5.5.Queue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.5.6.Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Chapter7.InternalModularity . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 7.1.Detailingtheconceptofprocedure. . . . . . . . . . . . . . . . . . . . . . 119 7.1.1.Simplecall. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 7.1.2.Nestedcalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 7.1.3.“Redwire”example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.2.Procedurearguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 7.2.1.Usefulnessofarguments. . . . . . . . . . . . . . . . . . . . . . . . . . 123 7.2.2.Argumentsbyvalueandbyreference. . . . . . . . . . . . . . . . . . 123 7.2.3.Passingargumentsbygeneralregisters. . . . . . . . . . . . . . . . . 123 7.2.4.Passingargumentsbyastack. . . . . . . . . . . . . . . . . . . . . . . 126 7.2.5.Passingargumentsbythesystemstack. . . . . . . . . . . . . . . . . 133 7.2.6.Ontheartofmixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 7.3.Localdata. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 7.3.1.Simplereservationoflocaldata . . . . . . . . . . . . . . . . . . . . . 137 7.3.2.Usingachainedlist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Chapter8.ManagingExceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . 147 8.1.WhathappensduringReset?. . . . . . . . . . . . . . . . . . . . . . . . . . 148 8.2.Possibleexceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 8.2.1.Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 8.2.2.Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 8.3.Prioritymanagement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.3.1.Prioritylevelsandsublevels . . . . . . . . . . . . . . . . . . . . . . . 162 8.3.2.Thenestedmechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . 166 8.4.Entryandreturninexceptionprocessing . . . . . . . . . . . . . . . . . . 167 8.4.1.Re-routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 8.4.2.Return. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 viii AssemblyLanguageProgramming 8.4.3.“Tail-chaining”and“Late-arriving”. . . . . . . . . . . . . . . . . . . 169 8.4.4.OtherusefulregistersfortheNVIC . . . . . . . . . . . . . . . . . . . 170 Chapter9.FromListingtoExecutable: ExternalModularity. . . . . . . . 173 9.1.Externalmodularity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 9.1.1.Genericexample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 9.1.2.Assemblybypieces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 9.1.3.Advantagesofassemblybypieces. . . . . . . . . . . . . . . . . . . . 178 9.1.4.Externalsymbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 9.1.5.IMPORTandEXPORTdirectives . . . . . . . . . . . . . . . . . . . . 181 9.2.Theroleoftheassembler. . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 9.2.1.Filesproducedbytheassembler . . . . . . . . . . . . . . . . . . . . . 183 9.2.2.Placementcounters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 9.2.3.Firstpass:symboltable . . . . . . . . . . . . . . . . . . . . . . . . . . 185 9.2.4.Secondpass:translation. . . . . . . . . . . . . . . . . . . . . . . . . . 186 9.2.5.Relocationtable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 9.3.Theroleofthelinker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 9.3.1.Functioningprinciple . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 9.3.2.Theproductsofthelinker. . . . . . . . . . . . . . . . . . . . . . . . . 190 9.4.Theloaderandthedebuggingunit . . . . . . . . . . . . . . . . . . . . . . 196 Appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 AppendixA.InstructionSet–AlphabeticalList. . . . . . . . . . . . . . . . . 201 AppendixB.TheSysTickTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 AppendixC.Exampleofa“Bootstrap”File. . . . . . . . . . . . . . . . . . . . 217 AppendixD.TheGNUAssembler. . . . . . . . . . . . . . . . . . . . . . . . . . 227 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

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ARM designs the cores of microcontrollers which equip most "embedded systems" based on 32-bit processors. Cortex M3 is one of these designs, recently developed by ARM with microcontroller applications in mind. To conceive a particularly optimized piece of software (as is often the case in the world
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ARM designs the cores of microcontrollers which equip most "embedded systems" based on 32-bit processors. Cortex M3 is one of these designs, recently developed by ARM with microcontroller applications in mind. To conceive a particularly optimized piece of software (as is often the case in the world

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