aspects of balanced ternary arithmetics implemented using cmos recharged semi-floating gate ...

124 Pages·2008·2.49 MB·English

ASPECTS OF BALANCED TERNARY
ARITHMETICS IMPLEMENTED USING
CMOS RECHARGED SEMI-FLOATING GATE
DEVICES
Ph.D. thesis
Henning Gundersen
May 2008

Acknowledgments
This thesis is a part of my work for my Ph.D. in Nanoelectronic at the Microelectronics
Systems Group (MES) at the Institute of Informatics at the University of Oslo. This
thesis is written using the powerful text processing language tool, LATEX
I want to thank all of my friends at the Microelectronics Systems Group, Ph.D. stu-
dents, master students and employees. During my years at the Department of Informatics
I met a lot of interesting people. Their humour really kept me going. Furthermore a
lot of funny and not always relevant discussions with H˚avard K. Riis and Johannes G.
Lomsdalen made life memorable.
I especially would like to thank my supervisor, Professor Yngvar Berg, for never losing
faith, my co-advisor, Dag T. Wisland, Snorre Aunet, for his academic and non-academic
discussions,TorSverre’Bassen’Lande,forhisknowledgeinanalogdesign,myfriendBjørn
Solberg, for proof reading, my colleagues at Telenor, my patience and helpful wife Heidi
for support and love and last but not least my two lovely daughters Ina and Matilde for
their patience and understanding when I was not there.
Blindern, May 19, 2008
Henning Gundersen
I
II
Abstract
Mostly all electronics used in computers today are based on binary logic. However, does
the binary logic have the capacity to be the leading technology in the future? Thus I raise
the question: why not use ternary logic? The optimal base for developing hardware is
proven to be 2.71. The closest integer to this optimal base is base 3, which corresponds to
the ternary numbering system. This thought is not new to computer scientists. In 1958 a
ternary computer was built in Russia, and as early as 1840 a self-taught English mathe-
matician, Thomas Fowler, invented a ternary calculating machine. This thesis deals with
some novel applications which can benefit from using ternary logic in current computer
designs.
I have proposed several ternary circuit designs. The circuits are implemented using
recharged semi-floating gate (RSFG) CMOS transistors. A novel balanced ternary adder
seems to be the most promising one. This new adder can directly replace any ordinary
binary solution. These applications can use any available CMOS process and no post pro-
cessing is needed, but for the moment there are some limitations. This is novel technology
which needs some more research to reach the robustness level of current designs.
Currentlyitdoesnotexist, electroniccomponentswhichinitsnaturehavethreestable
states. Binary logic uses transistors which can be switched ’on’ or ’off’. At the moment,
this is a limitation in the relation to the development of ternary architectures. However,
my qualified guess is that ternary logic will be a leading technology in the future.
III
IV
Contents
1 INTRODUCTION 1
1.1 Main Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.1 List of Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Overview of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 FLOATING GATE TRANSISTORS 5
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Floating Gate (FG) MOS Transistor . . . . . . . . . . . . . . . . . . . . . . 6
2.2.1 The Floating Gate Capacitors . . . . . . . . . . . . . . . . . . . . . . 7
2.2.2 Capacitive Voltage Division Model . . . . . . . . . . . . . . . . . . . 7
2.2.3 Charge Loss on the Floating Gate Node . . . . . . . . . . . . . . . . 8
2.2.4 Inverter Based Structures . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.5 Split-Gate Inverter Structure . . . . . . . . . . . . . . . . . . . . . . 9
2.2.6 Common Gate Inverter Structure . . . . . . . . . . . . . . . . . . . . 9
2.3 Non-Volatile FG Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.1 Fowler Nordheim Tunneling . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.2 Hot Carrier Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.3 UV Activated Programming . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Volatile FG Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.1 Recharged Floating Gate . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.2 Pseudo Floating Gate . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.3 Recharged Semi-Floating Gate . . . . . . . . . . . . . . . . . . . . . 12
2.4.4 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5 Auto-Zero Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.1 Removing the Auto-Zero Clock Signal . . . . . . . . . . . . . . . . . 13
2.6 Limitations Using 90nm CMOS Technology . . . . . . . . . . . . . . . . . . 13
2.6.1 Max Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.6.2 Parasitic Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6.3 Gate Leakage in Thin Oxide Layers . . . . . . . . . . . . . . . . . . 14
2.7 Measurement and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.7.1 Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
V
VI CONTENTS
3 MULTIPLE-VALUED TECHNOLOGY 19
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.1 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2 Multiple-Valued Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.1 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.2 Radix and Complexity . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.4 Noise Margins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.5 Completeness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.6 MVL-Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.7 Logic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.8 Down Literal Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.9 Pass Gate Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.10 Voltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.11 Max and Min Functions . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3 Measurement and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4 TERNARY LOGIC 31
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2 The Balanced Ternary Numbering System . . . . . . . . . . . . . . . . . . . 32
4.3 Search Trees Using Balanced Ternary Notaion . . . . . . . . . . . . . . . . . 33
4.3.1 The More, Less or Equal (MLE) Circuit . . . . . . . . . . . . . . . . 33
4.4 Signal Refreshment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.4.1 A Ternary Switching Element . . . . . . . . . . . . . . . . . . . . . . 34
4.5 Fault Tolerant Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.6 Measurement and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5 TERNARY ARITHMETICS 39
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1.1 Balanced Ternary Addition . . . . . . . . . . . . . . . . . . . . . . . 39
5.1.2 Balanced Ternary Multiplication . . . . . . . . . . . . . . . . . . . . 41
5.1.3 Balanced Ternary Division . . . . . . . . . . . . . . . . . . . . . . . 41
5.2 Balanced Ternary Adder Implementation . . . . . . . . . . . . . . . . . . . 42
5.2.1 Fast Addition Using Balanced Ternary Notation . . . . . . . . . . . 42
5.3 A Balanced Ternary Multiplication Circuit . . . . . . . . . . . . . . . . . . 43
5.4 Measurement and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6 CONCLUSIONS AND FUTURE WORK 47
6.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.1 Ternary Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.2 Ternary Adder Structures . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.3 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1.4 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
CONTENTS VII
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7 PUBLICATIONS 49
7.1 PAPER I: Max and Min Functions Using Multiple-Valued Recharged Semi-
Floating Gate Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.2 PAPER II: A Novel Ternary Switching Element Using CMOS Recharged
Semi-Floating Gate Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.3 PAPERIII:ANovelTernaryMore,LessandEqualityCircuitUsingRecharged
Semi-Floating Gate Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.4 PAPER IV: Fault Tolerant CMOS Logic Using Ternary Gates . . . . . . . . 71
7.5 PAPERV:ANovelBalancedTernaryAdderUsingRechargedSemi-Floating
Gate Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.6 PAPERVI:FastAdditionUsingBalancedTernaryCountersDesignedwith
CMOS Semi-Floating Gate Devices . . . . . . . . . . . . . . . . . . . . . . . 85
7.7 PAPER VII: A Balanced Ternary Multiplication Circuit Using Recharged
Semi-Floating Gate Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
A ADDITIONAL INFORMATION 99
A.1 Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
A.1.1 Instruments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
A.1.2 The Prototype Printed Circuit Board . . . . . . . . . . . . . . . . . 102
B ABBREVIATIONS 105
VIII CONTENTS