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ARM® Cortex®-A75 Core Revision: r2p0 Technical Reference Manual Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved. ARM 100403_0200_00_en ARM® Cortex®-A75 Core ARM® Cortex®-A75 Core Technical Reference Manual Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved. Release Information Document History Issue Date Confidentiality Change 0000-00 30 September 2016 Confidential First release for r0p0 0100-00 12 December 2016 Confidential First release for r1p0 0200-00 03 June 2017 Non-Confidential First release for r2p0 Non-Confidential Proprietary Notice This document is protected by copyright and other related rights and the practice or implementation of the information contained in this document may be protected by one or more patents or pending patent applications. No part of this document may be reproduced in any form by any means without the express prior written permission of ARM. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated. Your access to the information in this document is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations infringe any third party patents. THIS DOCUMENT IS PROVIDED “AS IS”. ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, SATISFACTORY QUALITY, NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE WITH RESPECT TO THE DOCUMENT. For the avoidance of doubt, ARM makes no representation with respect to, and has undertaken no analysis to identify or understand the scope and content of, third party patents, copyrights, trade secrets, or other rights. This document may include technical inaccuracies or typographical errors. TO THE EXTENT NOT PROHIBITED BY LAW, IN NO EVENT WILL ARM BE LIABLE FOR ANY DAMAGES, INCLUDING WITHOUT LIMITATION ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, ARISING OUT OF ANY USE OF THIS DOCUMENT, EVEN IF ARM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. This document consists solely of commercial items. You shall be responsible for ensuring that any use, duplication or disclosure of this document complies fully with any relevant export laws and regulations to assure that this document or any portion thereof is not exported, directly or indirectly, in violation of such export laws. Use of the word “partner” in reference to ARM’s customers is not intended to create or refer to any partnership relationship with any other company. ARM may make changes to this document at any time and without notice. If any of the provisions contained in these terms conflict with any of the provisions of any signed written agreement covering this document with ARM, then the signed written agreement prevails over and supersedes the conflicting provisions of these terms. This document may be translated into other languages for convenience, and you agree that if there is any conflict between the English version of this document and any translation, the terms of the English version of the Agreement shall prevail. Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM Limited or its affiliates in the EU and/or elsewhere. All rights reserved. Other brands and names mentioned in this document may be the trademarks of their respective owners. Please follow ARM’s trademark usage guidelines at http://www.arm.com/about/trademark-usage-guidelines.php Copyright © 2016, 2017, ARM Limited or its affiliates. All rights reserved. ARM Limited. Company 02557590 registered in England. 110 Fulbourn Road, Cambridge, England CB1 9NJ. LES-PRE-20349 ARM 100403_0200_00_en Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved. 2 Non-Confidential ARM® Cortex®-A75 Core Confidentiality Status This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to. Unrestricted Access is an ARM internal classification. Product Status The information in this document is Final, that is for a developed product. Web Address http://www.arm.com ARM 100403_0200_00_en Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved. 3 Non-Confidential Contents ARM® Cortex®-A75 Core Technical Reference Manual Preface About this book .......................................................................................................... 18 Feedback .................................................................................................................... 23 Part A Functional Description Chapter A1 Introduction A1.1 About the core ...................................................................................................... A1-28 A1.2 Features ................................................................................................................ A1-29 A1.3 Implementation options ........................................................................................ A1-30 A1.4 Supported standards and specifications .............................................................. A1-31 A1.5 Test features .......................................................................................................... A1-32 A1.6 Design tasks .......................................................................................................... A1-33 A1.7 Product revisions .................................................................................................. A1-34 Chapter A2 Technical Overview A2.1 Components .......................................................................................................... A2-36 A2.2 Interfaces .............................................................................................................. A2-38 A2.3 About system control ............................................................................................ A2-39 A2.4 About the Generic Timer ...................................................................................... A2-40 ARM 100403_0200_00_en Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved. 5 Non-Confidential Chapter A3 Clocks, Resets, and Input Synchronization A3.1 About Clocks, Resets, and Input Synchronization ................................................ A3-42 A3.2 Asynchronous interface ........................................................................................ A3-43 Chapter A4 Power Management A4.1 About power management .................................................................................... A4-46 A4.2 Voltage domains .................................................................................................... A4-47 A4.3 Power domains .................................................................................................... A4-48 A4.4 Architectural clock gating modes .......................................................................... A4-51 A4.5 Power control ........................................................................................................ A4-52 A4.6 Core power modes ................................................................................................ A4-53 A4.7 Encoding for power modes .................................................................................. A4-56 A4.8 Power domain states for power modes ................................................................ A4-57 A4.9 Power up and down sequences ............................................................................ A4-58 A4.10 Debug over powerdown ........................................................................................ A4-59 Chapter A5 Memory Management Unit A5.1 About the MMU .................................................................................................... A5-62 A5.2 TLB organization .................................................................................................. A5-64 A5.3 TLB match process .............................................................................................. A5-66 A5.4 Translation table walks .......................................................................................... A5-67 A5.5 MMU memory accesses ........................................................................................ A5-68 A5.6 Specific behaviors on aborts and memory attributes ............................................ A5-69 Chapter A6 Level 1 Memory System A6.1 About the L1 memory system .............................................................................. A6-72 A6.2 Cache behavior .................................................................................................... A6-73 A6.3 L1 instruction memory system .............................................................................. A6-75 A6.4 L1 data memory system ........................................................................................ A6-77 A6.5 Data prefetching .................................................................................................... A6-79 A6.6 Direct access to internal memory .......................................................................... A6-80 Chapter A7 Level 2 Memory System A7.1 About the L2 memory system .............................................................................. A7-94 A7.2 About the L2 cache .............................................................................................. A7-95 A7.3 Support for memory types .................................................................................... A7-96 Chapter A8 Reliability, Availability, and Serviceability (RAS) A8.1 Cache ECC and parity .......................................................................................... A8-98 A8.2 Cache protection behavior .................................................................................. A8-99 A8.3 Uncorrected errors and data poisoning .............................................................. A8-101 A8.4 RAS error types .................................................................................................. A8-102 A8.5 Error Synchronization Barrier ............................................................................ A8-103 A8.6 Error recording .................................................................................................... A8-104 A8.7 Error injection ...................................................................................................... A8-107 Chapter A9 Generic Interrupt Controller CPU Interface A9.1 About the Generic Interrupt Controller CPU Interface ........................................ A9-110 A9.2 Bypassing the CPU Interface .............................................................................. A9-111 ARM 100403_0200_00_en Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved. 6 Non-Confidential Chapter A10 Advanced SIMD and Floating-point Support A10.1 About the Advanced SIMD and floating-point support ...................................... A10-114 A10.2 Accessing the feature identification registers .................................................... A10-115 Part B Register Descriptions Chapter B1 AArch32 system registers B1.1 AArch32 registers ................................................................................................ B1-122 B1.2 AArch32 architectural system register summary ................................................ B1-123 B1.3 AArch32 implementation defined register summary .......................................... B1-129 B1.4 AArch32 registers by functional group ................................................................ B1-131 B1.5 ACTLR, Auxiliary Control Register ...................................................................... B1-136 B1.6 ACTLR2, Auxiliary Control Register 2 ................................................................ B1-138 B1.7 ADFSR, Auxiliary Data Fault Status Register .................................................... B1-139 B1.8 AIDR, Auxiliary ID Register ................................................................................ B1-140 B1.9 AIFSR, Auxiliary Instruction Fault Status Register .............................................. B1-141 B1.10 AMAIR0, Auxiliary Memory Attribute Indirection Register 0 ................................ B1-142 B1.11 AMAIR1, Auxiliary Memory Attribute Indirection Register 1 ................................ B1-143 B1.12 CCSIDR, Cache Size ID Register ...................................................................... B1-144 B1.13 CLIDR, Cache Level ID Register ........................................................................ B1-146 B1.14 CPACR, Architectural Feature Access Control Register .................................... B1-148 B1.15 CPUACTLR, CPU Auxiliary Control Register ...................................................... B1-149 B1.16 CPUACTLR2, CPU Auxiliary Control Register 2 ................................................ B1-151 B1.17 CPUCFR, CPU Configuration Register .............................................................. B1-153 B1.18 CPUECTLR, CPU Extended Control Register .................................................... B1-155 B1.19 CPUPCR, CPU Private Control Register ............................................................ B1-158 B1.20 CPUPMR, CPU Private Mask Register .............................................................. B1-160 B1.21 CPUPOR, CPU Private Operation Register ........................................................ B1-162 B1.22 CPUPSELR, CPU Private Selection Register .................................................... B1-164 B1.23 CPUPWRCTLR, CPU Power Control Register .................................................. B1-166 B1.24 CSSELR, Cache Size Selection Register .......................................................... B1-168 B1.25 CTR, Cache Type Register ................................................................................ B1-169 B1.26 DFSR, Data Fault Status Register ...................................................................... B1-171 B1.27 DISR, Deferred Interrupt Status Register ............................................................ B1-173 B1.28 ERRIDR, Error ID Register ................................................................................ B1-176 B1.29 ERRSELR, Error Record Select Register .......................................................... B1-177 B1.30 ERXADDR, Selected Error Record Address Register ........................................ B1-178 B1.31 ERXADDR2, Selected Error Record Address Register 2 .................................. B1-179 B1.32 ERXCTLR, Selected Error Record Control Register .......................................... B1-180 B1.33 ERXCTLR2, Selected Error Record Control Register 2 ...................................... B1-181 B1.34 ERXFR, Selected Error Record Feature Register .............................................. B1-182 B1.35 ERXFR2, Selected Error Record Feature Register 2 .......................................... B1-183 B1.36 ERXMISC0, Selected Error Miscellaneous Register 0 ...................................... B1-184 B1.37 ERXMISC1, Selected Error Miscellaneous Register 1 ........................................ B1-185 B1.38 ERXMISC2, Selected Error Record Miscellaneous Register 2 .......................... B1-186 B1.39 ERXMISC3, Selected Error Record Miscellaneous Register 3 .......................... B1-187 B1.40 ERXPFGCDNR, Selected Error Pseudo Fault Generation Count Down Register .... ............................................................................................................................. B1-188 B1.41 ERXPFGCTLR, Selected Error Pseudo Fault Generation Control Register ...... B1-190 ARM 100403_0200_00_en Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved. 7 Non-Confidential B1.42 ERXPFGFR, Selected Pseudo Fault Generation Feature Register .................... B1-192 B1.43 ERXSTATUS, Selected Error Record Primary Status Register .......................... B1-193 B1.44 FCSEIDR, FCSE Process ID Register ................................................................ B1-194 B1.45 HACR, Hyp Auxiliary Configuration Register ...................................................... B1-195 B1.46 HACTLR, Hyp Auxiliary Control Register ............................................................ B1-196 B1.47 HACTLR2, Hyp Auxiliary Control Register 2 ...................................................... B1-198 B1.48 HADFSR, Hyp Auxiliary Data Fault Status Syndrome Register .......................... B1-199 B1.49 HAIFSR, Hyp Auxiliary Instruction Fault Status Syndrome Register .................. B1-200 B1.50 HAMAIR0, Hyp Auxiliary Memory Attribute Indirection Register 0 ...................... B1-201 B1.51 HAMAIR1, Hyp Auxiliary Memory Attribute Indirection Register 1 ...................... B1-202 B1.52 HCR, Hyp Configuration Register ...................................................................... B1-203 B1.53 HCR2, Hyp Configuration Register 2 .................................................................. B1-205 B1.54 HSCTLR, Hyp System Control Register ............................................................ B1-206 B1.55 HSR, Hyp Syndrome Register ............................................................................ B1-208 B1.56 HTTBR, Hyp Translation Table Base Register .................................................... B1-210 B1.57 ID_AFR0, Auxiliary Feature Register 0 .............................................................. B1-211 B1.58 ID_DFR0, Debug Feature Register 0 .................................................................. B1-212 B1.59 ID_ISAR0, Instruction Set Attribute Register 0 .................................................. B1-214 B1.60 ID_ISAR1, Instruction Set Attribute Register 1 .................................................. B1-216 B1.61 ID_ISAR2, Instruction Set Attribute Register 2 .................................................. B1-218 B1.62 ID_ISAR3, Instruction Set Attribute Register 3 .................................................. B1-220 B1.63 ID_ISAR4, Instruction Set Attribute Register 4 .................................................. B1-222 B1.64 ID_ISAR5, Instruction Set Attribute Register 5 .................................................. B1-224 B1.65 ID_ISAR6, Instruction Set Attribute Register 6 .................................................. B1-226 B1.66 ID_MMFR0, Memory Model Feature Register 0 ................................................ B1-227 B1.67 ID_MMFR1, Memory Model Feature Register 1 ................................................ B1-229 B1.68 ID_MMFR2, Memory Model Feature Register 2 ................................................ B1-231 B1.69 ID_MMFR3, Memory Model Feature Register 3 ................................................ B1-233 B1.70 ID_MMFR4, Memory Model Feature Register 4 ................................................ B1-235 B1.71 ID_PFR0, Processor Feature Register 0 ............................................................ B1-237 B1.72 ID_PFR1, Processor Feature Register 1 ............................................................ B1-238 B1.73 IFSR, Instruction Fault Status Register .............................................................. B1-240 B1.74 MIDR, Main ID Register .................................................................................... B1-242 B1.75 MPIDR, Multiprocessor Affinity Register ............................................................ B1-243 B1.76 MVBAR, Monitor Vector Base Address Register ................................................ B1-245 B1.77 NSACR, Non-Secure Access Control Register .................................................. B1-246 B1.78 PAR, Physical Address Register ........................................................................ B1-247 B1.79 REVIDR, Revision ID Register ............................................................................ B1-249 B1.80 RVBAR, Reset Vector Base Address Register .................................................. B1-250 B1.81 SCR, Secure Configuration Register .................................................................. B1-251 B1.82 SCTLR, System Control Register ...................................................................... B1-252 B1.83 SDCR, Secure Debug Control Register .............................................................. B1-255 B1.84 TTBCR, Translation Table Base Control Register .............................................. B1-257 B1.85 TTBR0, Translation Table Base Register 0 ........................................................ B1-258 B1.86 TTBR1, Translation Table Base Register 1 ........................................................ B1-260 B1.87 VBAR, Vector Base Address Register ................................................................ B1-262 B1.88 VDFSR, Virtual SError Exception Syndrome Register ........................................ B1-263 B1.89 VDISR, Virtual Deferred Interrupt Status Register .............................................. B1-264 B1.90 VMPIDR, Virtualization Multiprocessor ID Register ............................................ B1-267 B1.91 VPIDR, Virtualization Processor ID Register ...................................................... B1-268 ARM 100403_0200_00_en Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved. 8 Non-Confidential B1.92 VTCR, Virtualization Translation Control Register .............................................. B1-269 B1.93 VTTBR, Virtualization Translation Table Base Register ...................................... B1-272 Chapter B2 AArch64 system registers B2.1 AArch64 registers ................................................................................................ B2-276 B2.2 AArch64 architectural system register summary ................................................ B2-277 B2.3 AArch64 implementation defined register summary .......................................... B2-284 B2.4 AArch64 registers by functional group ................................................................ B2-286 B2.5 ACTLR_EL1, Auxiliary Control Register, EL1 .................................................... B2-293 B2.6 ACTLR_EL2, Auxiliary Control Register, EL2 .................................................... B2-294 B2.7 ACTLR_EL3, Auxiliary Control Register, EL3 .................................................... B2-296 B2.8 AFSR0_EL1, Auxiliary Fault Status Register 0, EL1 .......................................... B2-298 B2.9 AFSR0_EL2, Auxiliary Fault Status Register 0, EL2 .......................................... B2-299 B2.10 AFSR0_EL3, Auxiliary Fault Status Register 0, EL3 .......................................... B2-300 B2.11 AFSR1_EL1, Auxiliary Fault Status Register 1, EL1 .......................................... B2-301 B2.12 AFSR1_EL2, Auxiliary Fault Status Register 1, EL2 .......................................... B2-302 B2.13 AFSR1_EL3, Auxiliary Fault Status Register 1, EL3 .......................................... B2-303 B2.14 AIDR_EL1, Auxiliary ID Register, EL1 ................................................................ B2-304 B2.15 AMAIR_EL1, Auxiliary Memory Attribute Indirection Register, EL1 .................... B2-305 B2.16 AMAIR_EL2, Auxiliary Memory Attribute Indirection Register, EL2 .................... B2-306 B2.17 AMAIR_EL3, Auxiliary Memory Attribute Indirection Register, EL3 .................... B2-307 B2.18 CCSIDR_EL1, Cache Size ID Register, EL1 ...................................................... B2-308 B2.19 CLIDR_EL1, Cache Level ID Register, EL1 ...................................................... B2-310 B2.20 CPACR_EL1, Architectural Feature Access Control Register, EL1 .................... B2-312 B2.21 CPTR_EL2, Architectural Feature Trap Register, EL2 ........................................ B2-313 B2.22 CPTR_EL3, Architectural Feature Trap Register, EL3 ........................................ B2-314 B2.23 CPUACTLR_EL1, CPU Auxiliary Control Register, EL1 .................................... B2-315 B2.24 CPUACTLR2_EL1, CPU Auxiliary Control Register 2, EL1 ................................ B2-317 B2.25 CPUCFR_EL1, CPU Configuration Register, EL1 .............................................. B2-319 B2.26 CPUECTLR_EL1, CPU Extended Control Register, EL1 .................................. B2-321 B2.27 CPUPCR_EL3, CPU Private Control Register, EL3 ............................................ B2-324 B2.28 CPUPMR_EL3, CPU Private Mask Register, EL3 .............................................. B2-326 B2.29 CPUPOR_EL3, CPU Private Operation Register, EL3 ...................................... B2-328 B2.30 CPUPSELR_EL3, CPU Private Selection Register, EL3 .................................... B2-330 B2.31 CPUPWRCTLR_EL1, Power Control Register, EL1 .......................................... B2-332 B2.32 CSSELR_EL1, Cache Size Selection Register, EL1 .......................................... B2-334 B2.33 CTR_EL0, Cache Type Register, EL0 ................................................................ B2-335 B2.34 DCZID_EL0, Data Cache Zero ID Register, EL0 ................................................ B2-337 B2.35 DISR_EL1, Deferred Interrupt Status Register, EL1 .......................................... B2-338 B2.36 ERRIDR_EL1, Error ID Register, EL1 ................................................................ B2-340 B2.37 ERRSELR_EL1, Error Record Select Register, EL1 .......................................... B2-341 B2.38 ERXADDR_EL1, Selected Error Record Address Register, EL1 ........................ B2-342 B2.39 ERXCTLR_EL1, Selected Error Record Control Register, EL1 .......................... B2-343 B2.40 ERXFR_EL1, Selected Error Record Feature Register, EL1 .............................. B2-344 B2.41 ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0, EL1 .......... B2-345 B2.42 ERXMISC1_EL1, Selected Error Record Miscellaneous Register 1, EL1 .......... B2-346 B2.43 ERXPFGCDNR_EL1, Selected Error Pseudo Fault Generation Count Down Register, EL1 ...................................................................................................................... B2-347 B2.44 ERXPFGCTLR_EL1, Selected Error Pseudo Fault Generation Control Register, EL1 ... ............................................................................................................................. B2-349 ARM 100403_0200_00_en Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved. 9 Non-Confidential B2.45 ERXPFGFR_EL1, Selected Pseudo Fault Generation Feature Register, EL1 .. B2-351 B2.46 ERXSTATUS_EL1, Selected Error Record Primary Status Register, EL1 .......... B2-352 B2.47 ESR_EL1, Exception Syndrome Register, EL1 .................................................. B2-353 B2.48 ESR_EL2, Exception Syndrome Register, EL2 .................................................. B2-354 B2.49 ESR_EL3, Exception Syndrome Register, EL3 .................................................. B2-355 B2.50 HACR_EL2, Hyp Auxiliary Configuration Register, EL2 ...................................... B2-356 B2.51 HCR_EL2, Hypervisor Configuration Register, EL2 ............................................ B2-357 B2.52 ID_AA64AFR0_EL1, AArch64 Auxiliary Feature Register 0 .............................. B2-359 B2.53 ID_AA64AFR1_EL1, AArch64 Auxiliary Feature Register 1 .............................. B2-360 B2.54 ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0, EL1 ........................ B2-361 B2.55 ID_AA64DFR1_EL1, AArch64 Debug Feature Register 1, EL1 ........................ B2-363 B2.56 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0, EL1 .......... B2-364 B2.57 ID_AA64ISAR1_EL1, AArch64 Instruction Set Attribute Register 1, EL1 .......... B2-366 B2.58 ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0, EL1 ........ B2-367 B2.59 ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1, EL1 ........ B2-369 B2.60 ID_AA64MMFR2_EL1, AArch64 Memory Model Feature Register 2, EL1 ........ B2-371 B2.61 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1 .................... B2-372 B2.62 ID_AFR0_EL1, AArch32 Auxiliary Feature Register 0, EL1 .............................. B2-374 B2.63 ID_DFR0_EL1, AArch32 Debug Feature Register 0, EL1 .................................. B2-375 B2.64 ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0, EL1 .................... B2-377 B2.65 ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1, EL1 .................... B2-379 B2.66 ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2, EL1 .................... B2-381 B2.67 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1 .................... B2-383 B2.68 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1 .................... B2-385 B2.69 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1 .................... B2-387 B2.70 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1 .................... B2-389 B2.71 ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0, EL1 .................. B2-390 B2.72 ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1, EL1 .................. B2-392 B2.73 ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2, EL1 .................. B2-394 B2.74 ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3, EL1 .................. B2-396 B2.75 ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4, EL1 .................. B2-398 B2.76 ID_PFR0_EL1, AArch32 Processor Feature Register 0, EL1 ............................ B2-400 B2.77 ID_PFR1_EL1, AArch32 Core Feature Register 1, EL1 .................................... B2-401 B2.78 IFSR32_EL2, Instruction Fault Status Register, EL2 .......................................... B2-402 B2.79 LORC_EL1, LORegion Control Register, EL1 .................................................... B2-404 B2.80 LORID_EL1, LORegion ID Register, EL1 .......................................................... B2-405 B2.81 LORN_EL1, LORegion Number Register, EL1 .................................................. B2-406 B2.82 MDCR_EL3, Monitor Debug Configuration Register, EL3 .................................. B2-407 B2.83 MIDR_EL1, Main ID Register, EL1 ...................................................................... B2-409 B2.84 MPIDR_EL1, Multiprocessor Affinity Register, EL1 ............................................ B2-410 B2.85 PAR_EL1, Physical Address Register, EL1 ........................................................ B2-412 B2.86 REVIDR_EL1, Revision ID Register, EL1 .......................................................... B2-413 B2.87 RMR_EL3, Reset Management Register ............................................................ B2-414 B2.88 RVBAR_EL3, Reset Vector Base Address Register, EL3 .................................. B2-416 B2.89 SCTLR_EL1, System Control Register, EL1 ...................................................... B2-417 B2.90 SCTLR_EL2, System Control Register, EL2 ...................................................... B2-419 B2.91 SCTLR_EL3, System Control Register, EL3 ...................................................... B2-420 B2.92 TCR_EL1, Translation Control Register, EL1 ...................................................... B2-422 B2.93 TCR_EL2, Translation Control Register, EL2 ...................................................... B2-423 B2.94 TCR_EL3, Translation Control Register, EL3 ...................................................... B2-424 ARM 100403_0200_00_en Copyright © 2016, 2017 ARM Limited or its affiliates. All rights reserved. 10 Non-Confidential

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ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile (ARM DDI. 0487). • AMBA® AXI™ and . The Cortex-A75 core is delivered as a synthesizable Register Transfer Level (RTL) description in Verilog. HDL. Before you can use the LDR pc, [r13], #imm. • LDM r13, {…pc}.

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