ARM Architecture Reference Manual (2nd Edition)

811 Pages·2001·12.65 MB·English

by  David Seal

ARM Architecture
Reference Manual
ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved.
Copyright © 1996–2000 ARM Limited. All rights reserved.
Release Information
The following changes have been made to this document.
Change History
Date Issue Change
February 1996 A First edition.
July 1997 B Updated and index added.
April 1998 C Updated.
February 2000 D Updated for ARM architecture v5.
June 2000 E Updated for ARM architecture v5TE and
corrections to Part B.
Proprietary Notice
ARM, the ARM Powered logo, Thumb, and StrongARM are registered trademarks of ARM Limited.
The ARM logo, AMBA, Angel, ARMulator, EmbeddedICE, ModelGen, Multi-ICE, PrimeCell, ARM7TDMI,
ARM7TDMI-S, ARM9TDMI, ARM9E-S, ETM7, ETM9, TDMI, STRONG, are trademarks of ARM Limited.
All other products or services mentioned herein may be trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted
or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars of the
product and its use contained in this document are given by ARM in good faith. However, all warranties implied or
expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss
or damage arising from the use of any information in this document, or any error or omission in such information, or any
incorrect use of the product.
ii Copyright © 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E
Preface
This preface describes the versions of the ARM architecture and the contents of this manual, then lists the
conventions and terminology it uses.
• About this manual on pageiv
• Architecture versions and variants on pagev
• Using this manual on pagex
• Conventions on pagexii.
ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. iii
Preface
About this manual
The purpose of this manual is to describe the ARM instruction set architecture, including its high code
density Thumb subset, and two of its standard coprocessor extensions:
• The standard System Control coprocessor (coprocessor 15), which is used to control memory system
components such as caches, write buffers, Memory Management Units, and Protection Units.
• The Vector Floating-point (VFP) architecture, which uses coprocessors 10 and 11 to supply a
high-performance floating-point instruction set.
These instruction sets are described primarily from the viewpoint of the instruction being a 32-bit word or
16-bit halfword. The precise effects of each instruction are described, including any restrictions on its use.
This information is of primary importance to authors of compilers, assemblers, and other programs that
generate ARM machine code.
Assembler syntax is given for most of the instructions described in this manual, allowing instructions to be
specified in textual form. This is of considerable use to assembly code writers, and also when debugging
either assembler or high-level language code at the single instruction level.
However, this manual is not intended as tutorial material for ARM assembler language, nor does it describe
ARM assembler language at anything other than a very basic level. To make effective use of ARM
assembler language, consult the documentation supplied with the assembler being used. Different
assemblers vary considerably with respect to many aspects of assembler language, such as which assembler
directives are accepted and how they are coded.
A considerable amount of generic information is also included about how ARM processors access memory
and other system components. Although this usually needs to be supplemented by detailed
implementation-specific information from the technical reference manual of the device being used, this
information is of use to designers of ARM-based systems.
iv Copyright © 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E
Preface
Architecture versions and variants
The ARM instruction set architecture has evolved significantly since it was first developed, and will
continue to be developed in the future. In order to be precise about which instructions exist in any particular
ARM implementation, five major versions of the instruction set have been defined to date. These are
denoted by the version numbers 1 to 5.
Many of the versions can be qualified with variant letters to specify collections of additional instructions
that are included in that version. These collections vary from being very small (the M variant denotes the
addition of just four extra instructions) to very large (the T variant denotes the addition of the entire Thumb
instruction set).
The five versions of the ARM instruction set architecture to date are as follows:
Version 1 This version was implemented only by ARM1, and was never used in a commercial product.
It contained:
• the basic data-processing instructions (not including multiplies)
• byte, word, and multi-word load/store instructions
• branch instructions, including a branch-and-link instruction designed for subroutine
calls
• a software interrupt instruction, for use in making Operating System calls.
Version 1 only had a 26-bit address space, and is now obsolete.
Version 2 This version extended architecture version 1 by adding:
• multiply and multiply-accumulate instructions
• coprocessor support
• two more banked registers in fast interrupt mode
• atomic load-and-store instructions called SWP and SWPB (in a slightly later variant
called version 2a).
Versions 2 and 2a still only had a 26-bit address space, and are now obsolete.
Version 3 This architecture version extended the addressing range to 32 bits. Program status
information which had previously been stored in R15 was moved to a new Current Program
Status Register (CPSR), and Saved Program Status Registers (SPSRs) were added to
preserve the CPSR contents when an exception occurred. As a result, the following changes
occurred to the instruction set:
• two instructions (MRS and MSR) were added to allow the new CPSR and SPSRs to be
accessed.
• the functionality of instructions previously used to return from exceptions was
modified to allow them to continue to be used for that purpose.
Version 3 also added two new processor modes in order to make it possible to use Data
Abort, Prefetch Abort and Undefined Instruction exceptions effectively in Operating
System code.
Backwards-compatibility support for the 26-bit architectures was obligatory in version 3,
except in a variant called version 3G. The distinction between versions 3 and 3G is now
obsolete.
ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. v
Preface
Version 4 This version extended architecture version 3 by adding:
• halfword load/store instructions
• instructions to load and sign-extend bytes and halfwords
• in T variants, an instruction to transfer to Thumb state
• a new privileged processor mode that uses the User mode registers.
Version 4 also made it clearer which instructions should cause the Undefined Instruction
exception to be taken.
Backwards-compatibility support for 26-bit architectures ceased to be obligatory in version
4.
Version 5 This version extends architecture version 4 by adding instructions and slightly modifying
the definitions of some existing instructions to:
• improve the efficiency of ARM/Thumb interworking in T variants
• allow the same code generation techniques to be used for non-T variants as for T
variants.
Version 5 also:
• adds a count leading zeros instruction, which (among other things) allows more
efficient integer divide and interrupt prioritization routines
• adds a software breakpoint instruction
• adds more instruction options for coprocessor designers
• tightens the definition of how flags are set by multiply instructions.
The Thumb instruction set (T variants)
The Thumb instruction set is a re-encoded subset of the ARM instruction set. Thumb instructions are half
the size of ARM instructions (16 bits compared with 32), with the result that greater code density can usually
be achieved by using the Thumb instruction set instead of the ARM instruction set. The Thumb instruction
set is described in detail in Chapter A6 The Thumb Instruction Set and Chapter A7 Thumb Instructions.
Two limitations of the Thumb instruction set compared with the ARM instruction set are:
• Thumb code usually uses more instructions for the same job, so ARM code is usually best for
maximizing the performance of time-critical code.
• The Thumb instruction set does not include some instructions that are needed for exception handling,
so ARM code needs to be used for at least the top-level exception handlers.
Because of the second of these, the Thumb instruction set is always used in conjunction with a suitable
version of the ARM instruction set. Its presence is denoted by the variant letter T, and it is not valid prior to
ARM architecture version 4.
vi Copyright © 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E
Preface
Thumb instruction set versions
There are two versions of the Thumb instruction set:
• Thumb version 1 is used in T variants of ARM architecture version 4
• Thumb version 2 is used in T variants of ARM architecture version 5.
Compared with Thumb version 1, Thumb version 2:
• adds instructions and slightly modifies the definition of some existing instructions to improve the
efficiency of ARM/Thumb interworking
• adds a software breakpoint instruction
• tightens the definition of how the Thumb multiply instruction sets the flags.
These improvements are closely related to the changes between ARM architecture versions 4 and 5.
Note
In general, the Thumb instruction set version number is not used in this manual. Instead, the version number
of the associated version of the ARM instruction set is used, to allow easy use with the naming scheme
described in Naming of ARM/Thumb architecture versions on pageviii.
Long multiply instructions (M variants)
M variants of the ARM instruction set include four extra instructions which perform 32 · 32 fi 64
multiplications and 32 · 32 + 64 fi 64 multiply-accumulates. These instructions imply the existence of a
multiplier that is significantly larger than minimum, and so are sometimes omitted in implementations for
which a small die size is very important and multiply performance is not very important. Their presence is
denoted by the use of the variant letter M.
These instructions were first defined as a variant of architecture version 3, and are included in similar
variants of later architecture versions. Because the combination of requirements that leads to them being
excluded does not arise very often in practice, inclusion of these instructions is standard in architecture
versions 4 and above.
Enhanced DSP instructions (E variants)
E variants of the ARM instruction set include a number of extra instructions which enhance the performance
of an ARM processor on typical digital signal processing (DSP) algorithms. These instructions are
described in detail in Chapter A10 Enhanced DSP Extension, and include:
• Several new multiply and multiply-accumulate instructions that act on 16-bit data items
• Addition and subtraction instructions that perform saturated signed arithmetic. This is a form of
integer arithmetic that produces the maximum negative or positive value instead of wrapping around
if the calculation overflows the normal integer range.
ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. vii
Preface
• Load (LDRD), store (STRD) and coprocessor register transfer (MCRR and MRRC) instructions that act
on 2 words of data.
• A cache preload instruction PLD.
These instructions were first defined as a variant of architecture version 5T. Their presence is denoted by
the variant letter E, and they are not valid prior to architecture version 5. They are also not valid in non-T
or non-M variants of the architecture.
The ARMv5TExP architecture version
Some early implementations of the enhanced DSP variant of the ARM architecture omitted the LDRD,
STRD, MCRR, MRRC and PLD instructions. Apart from this omission, all the ARM implementations
concerned implemented the ARMv5TE architecture.
In order to be able to name this architecture variant, the letter P can be used to exclude these five instructions
from architecture version ARMv5TE, according to the rules in Naming of ARM/Thumb architecture
versions on pageviii. The resulting architecture variant is therefore named ARMv5TExP. This is the only
use of the P variant letter.
Naming of ARM/Thumb architecture versions
To name a precise version and variant of the ARM/Thumb architecture, the following strings are
concatenated:
1. The string ARMv.
2. The version number of the ARM instruction set.
3. Variant letters of the included variants, except that the M variant is standard in architecture versions
4 and above, and therefore not normally listed.
4. If any variants described as standard in 3 above are not present, the letter x followed by the letters
of the excluded variants. In addition, the letter P can be used after x to denote the exclusion of certain
instructions from architecture version ARMv5TE, as described in The ARMv5TExP architecture
version.
The table Architecture versions on pageix lists the standard names of the current (not obsolete)
ARM/Thumb architecture versions described in this manual. These names provide a shorthand way of
describing the precise instruction set implemented by an ARM processor. However, this manual normally
uses descriptive phrases such as “M variants of architecture version 3 and above” to avoid the use of lists
of architecture names which are already long and will grow further in the future.
Obsolete architecture names are ARMv1, ARMv2, ARMv2a, and ARMv3G. These are the versions 1, 2,
2a, and 3G described in Architecture versions and variants on pagev.
viii Copyright © 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E
Preface
Architecture versions
ARM instruction Thumb instruction Long multiply Enhanced DSP
Name
set version set version instructions? instructions
ARMv3 3 None No No
ARMv3M 3 None Yes No
ARMv4xM 4 None No No
ARMv4 4 None Yes No
ARMv4TxM 4 1 No No
ARMv4T 4 1 Yes No
ARMv5xM 5 None No No
ARMv5 5 None Yes No
ARMv5TxM 5 2 No No
ARMv5T 5 2 Yes No
ARMv5TExP 5 2 Yes All but LDRD,
MCRR, MRRC,
PLD, and STRD
ARMv5TE 5 2 Yes Yes
ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. ix
Preface
Using this manual
The information in this manual is organized into three parts, as described below.
Part A - CPU Architectures
Part A describes the ARM and Thumb instruction sets, and contains the following chapters:
Chapter A1 Gives a quick overview of the ARM instruction set.
Chapter A2 Describes the types of value that ARM instructions operate on, the general-purpose registers
that contain those values, and the Program Status Registers. This chapter also describes how
ARM processors handle interrupts and other exceptions, and contains general information
about the memory interface of an ARM processor.
Chapter A3 Gives a description of the ARM instruction set, organized by type of instruction.
Chapter A4 Contains detailed reference material on each ARM instruction, arranged alphabetically by
instruction mnemonic.
Chapter A5 Contains detailed reference material on the addressing modes used by ARM instructions.
The term addressing mode is interpreted broadly in this manual, to mean a procedure shared
by many different instructions, for generating values used by the instructions. For four of
the addressing modes described in this chapter, the values generated are memory addresses
(which is the traditional role of an addressing mode). The remaining addressing mode
generates values to be used as operands by data-processing instructions.
Chapter A6 Gives a description of the Thumb instruction set, organized by type of instruction. This
chapter also contains information about how to switch between the ARM and Thumb
instruction sets, and how exceptions that arise during Thumb state execution are handled.
Chapter A7 Contains detailed reference material on each Thumb instruction, arranged alphabetically by
instruction mnemonic.
Chapter A8 Gives information on the 26-bit architectures (ARMv1, ARMv2, and ARMv2a), and about
the backwards-compatibility support for these architectures that is built into some later
ARM processors. All of these features are now obsolete, and information about them is only
relevant to historical systems.
Chapter A9 Contains some examples of using the ARM instruction set.
Chapter A10 Gives a description of the extra instructions added in the enhanced DSP extension (see
Enhanced DSP instructions (E variants) on pagevii).
x Copyright © 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E