Arithmetic optimization techniques for hardware and software design

199 Pages·2010·3.16 MB·English

by  Ryan Kastner

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Arithmetic Optimization Techniques for Hardware and Software Design
Obtain better system performance, lower energy consumption, and avoid hand-
coding arithmetic functions with this concise guide to automated optimization
techniques for hardware and software design. High-level compiler optimizations
andhigh-speedarchitecturesforimplementingFIRfiltersarecovered,whichcan
improve performance in communications, signal processing, computer graphics,
andcryptography.Clearlyexplainedalgorithmsandillustrativeexamplesthrough-
outmakeiteasytounderstandthetechniquesandwritesoftwarefortheirimple-
mentation.Backgroundinformationonthesynthesisofarithmeticexpressionsand
computer arithmetic is also included, making the book ideal for new-comers to
the subject. This is an invaluable resource for researchers, professionals, and
graduatestudentsworkinginsystemleveldesignandautomation,compilers,and
VLSICAD.
Ryan Kastner is an Associate Professor in the Department of Computer Science
and Engineering at the University of California, San Diego. He received his
Ph.D. in Computer Science from UCLA in 2002 and has since published over
100technicalpapersandthreebooks.Hiscurrentresearchinterestsareinembed-
ded system design, particularly the use of reconfigurable computing devices for
digital signal processing.
Anup Hosangadi is an R&D Engineer in the Emulation Group at Cadence Design
Systems,Inc.HereceivedhisPh.D.inComputerEngineeringfromtheUniversity
ofCalifornia,SantaBarbara,in2006andhisresearchinterestsincludehigh-level
synthesis, combinatorial optimization, and computer arithmetic.
Farzan Fallah is currently a visiting scholar at Stanford University, Stanford.
He received his Ph.D. in Electrical Engineering and Computer Science from MIT
in 1999, after which he worked as a Project Leader at Fujitsu Laboratories of
America in Sunnyvale until 2008. Farzan has published over 60 papers and has
20patentsgrantedorpending.HehasreceivedaBestPaperAwardattheDesign
Automation Conference in 1998 and a Best Paper Award at the VLSI Design
Conference in 2005. He is currently the cochair of the Low Power Technical
Committee of ACM SIGDA and an associate editor of the ACM Transactions on
Design Automation ofElectronic Systems.

Arithmetic Optimization
Techniques for Hardware
and Software Design
RYAN KASTNER
UniversityofCalifornia,SanDiego
ANUP HOSANGADI
CadenceDesignSystems,Inc.
FARZAN FALLAH
StanfordUniversity
CAMBRIDGEUNIVERSITYPRESS
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Cambridge University Press
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Published in the United States of America by Cambridge University Press, New York
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Information on this title: www.cambridge.org/9780521880992
© Cambridge University Press 2010
This publication is in copyright. Subject to statutory exception and to the
provision of relevant collective licensing agreements, no reproduction of any part
may take place without the written permission of Cambridge University Press.
First published in print format 2010
ISBN-13 978-0-511-71299-9 eBook (NetLibrary)
ISBN-13 978-0-521-88099-2 Hardback
Cambridge University Press has no responsibility for the persistence or accuracy
of urls for external or third-party internet websites referred to in this publication,
and does not guarantee that any content on such websites is, or will remain,
accurate or appropriate.
Contents
List ofabbreviations page vii
Preface ix
1 Introduction 1
1.1 Overview 1
1.2 Salientfeaturesof this book 5
1.3 Organization 6
1.4 Target audience 7
2 Use ofpolynomial expressions and linearsystems 9
2.1 Chapteroverview 9
2.2 Approximation algorithms 9
2.3 Computer graphics 10
2.4 Digital signal processing (DSP) 12
2.5 Cryptography 16
2.6 Addresscalculation in data intensive applications 17
2.7 Summary 19
3 Softwarecompilation 21
3.1 Chapteroverview 21
3.2 Basic software compilerstructure 21
3.3 Algebraic transformations inoptimizing software compilers 25
3.4 Summary 33
4 Hardwaresynthesis 35
4.1 Chapteroverview 35
4.2 Hardware synthesisdesign flow 35
4.3 System specification 38
4.4 Program representation 39
4.5 Algorithmic optimization 44
4.6 Resourceallocation 45
4.7 Operation scheduling 49
vi Contents
4.8 Resourcebinding 56
4.9 Case study: FIR filter 58
4.10 Summary 63
5 Fundamentalsof digital arithmetic 68
5.1 Chapter overview 68
5.2 Basic numberrepresentation 68
5.3 Two-operand addition 75
5.4 Multiple-operand addition 82
5.5 Summary 93
6 Polynomial expressions 95
6.1 Chapter overview 95
6.2 Polynomialexpressions 95
6.3 Problem formulation 96
6.4 Related optimization techniques 96
6.5 Algebraic optimization ofarithmetic expressions 99
6.6 Experimental results 113
6.7 Optimal solutions forreducing the number ofoperations
inarithmetic expressions 117
6.8 Summary 123
7 Linear systems 126
7.1 Chapter overview 126
7.2 Linear system basics 126
7.3 Problem formulation 129
7.4 Single-constant multiplication (SCM) 130
7.5 Multiple-constant multiplication (MCM) 133
7.6 Overview of linearsystemoptimizations 140
7.7 Transformation of alinear system into a polynomial expression 142
7.8 Optimization for synthesis using two-operand adders 143
7.9 FIR filter optimization 147
7.10 Synthesisfor multiple-operand addition 158
7.11 Delay-aware optimization 164
7.12 Software optimization 174
7.13 Summary 178
Index 182
Abbreviations
ACU address calculation units
ADPCM adaptive differential pulse-code modulation
AE address expression
AEB available expression blocks
ALAP as late as possible
ALU arithmetic logic unit
ASAP as soon as possible
ASIC application specific integrated circuit
AST abstractsyntaxtree
BSC binary-stored carry
CAX concurrent arithmetic extraction
CDFG control data flowgraph
CFG control flow graph
CIM cube intersectionmatrix
CLA carry look-ahead adder
CLB configurablelogic block
CLG carry look-ahead generator
CNF conjunctive normal form
CPA carry propagate adder
CSA carry save adder
CSD canonical signed digits
CSE common subexpressionelimination
DAG directed acyclic graph
DCT discretecosine transform
DFG dataflow graph
DFT discreteFourier transform
DHT discreteHartleytransform
DSP digitalsignal processor/processing
DST discretesine transform
DU define use
DWT discretewavelet transform
FDS force directed scheduling
FF flip flop
viii Listofabbreviations
FFT finiteFourier transform
FIR finiteimpulseresponse
FPGA fieldprogrammablegate array
FX fast-extract
HDL hardware description language
IDCT inverse discretecosine transform
IIR infinite impulseresponse
ILP integer linear programming
IMDCT inverse modifieddiscretecosine transform
IP intellectual property
KCM kernel-cubematrix
LUT look up table
MAC multiply accumulate
MCM multiple-constant multiplication
MDCT modified discrete cosine transform
MSPS million samples persecond
NP non-deterministic polynomial
PDA parallel distributedarithmetic
PDG program dependence graph
PRE partial redundancy elimination
RCA ripple carry adder
RCS resourceconstrained scheduling
RDFT real discrete Fourier transform
RTL register transfer level
SA simulatedannealing
SOP sumof products
SSA staticsingleassignment
TCS timingconstrained scheduling
THR tree height reduction
WHT Walsh–Hadamard transform