Arithmetic and logic in computer systems

269 Pages·2004·10.83 MB·English

by  Mi Lu

Arithmetic and Logic in
Computer Systems
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Arithmetic and Logic in
Computer Systems
Mi Lu
Texas A&M University
WILEY-
INTERSCIENCE
A JOHN WILEY & SONS, INC., PUBLICATION
Copyright 0 2004 by John Wiley & Sons, Inc. All rights reserved.
Published by John Wiley & Sons, Inc., Hoboken, New Jersey.
Published simultaneously in Canada.
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Library of Congress Cataloging-in-Publication Data is available.
ISBN 0-471-46945-9
Printed in the United States of America.
I 0 9 8 7 6 5 4 3 2 1
To the memory of my mother, Shu Sheng Fan.
To my father, Chong Pu Lu, my husband, Jiming Yin, and my son, Luke Yin.
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Contents
Preface xiii
List of Figures xv
List of Tables xix
About the Author xxi
1 Computer Number Systems 1
1.1 Conventional Radix Number System 2
1.2 Conversion of Radix Numbers 4
1.3 Representation of Signed Numbers 7
1.3.1 Sign-Magnitude 8
1.3.2 Diminished Radix Complement 8
1.3.3 Radix Complement 8
1.4 Signed-Digit Number System 11
1.5 Floating-point Number Representation 15
1.5.1 Normalization 15
1.5.2 Bias 16
1.6 Residue Number System 22
1.7 Logarithmic Number System 23
References 24
Problems 26
vii
viii CONTENTS
2 Addition and Subtraction 29
2.1 Single-Bit Adders 29
2.1.1 Logical Devices 29
2.1.2 Single-Bit Half-Adder and Full-Adders 32
2.2 Negation 35
2.2.1 Negation in One’s Complement System 36
2.2.2 Negation in Two’s Complement System 38
2.3 Subtraction through Addition 40
2.4 Overjflow 43
2.5 Ripple Carry Adders 44
2.5.1 Two’s Complement Addition 44
2.5.2 One’s Complement Addition 46
2.5.3 Sign-Magnitude Addition 48
References 50
Problems 52
3 High-speed Adder
53
3.1 Conditional-Sum Addition 53
3.2 Carry-Completion Sensing Addition 56
3.3 Carry-Lookahead Addition (CLA) 61
3.3.1 Carry-Lookahead Adder 61
3.3.2 Block Carry Lookahead Adder 62
3.4 Carry-Save Adders (CSA) 66
3.5 Bit-Partitioned Multiple Addition 71
References 73
Problems 74
4 Sequential Multiplication 77
4. 1 Add-and-shifl Approach 78
4.2 Indirect Multiplication Schemes 81
4.2. 1 Unsigned Number Multiplication 81
4.2.2 Sign-Magnitude Number Multiplication 81
4.2.3 One’s Complement Number Multiplication 81
4.2.4 Two’s Complement Number Multiplication 85
4.3 Robertson Signed Number Multiplication 87
’s
4.4 Recoding Technique 89
4.4. 1 Non-overlapped Multiple Bit Scanning 89
4.4.2 Overlapped Multiple Bit Scanning 90
CONTENTS ix
4.4.3 Booth’s Algorithm 93
4.4.4 Canonical Multiplier Recoding 95
References 99
Problems 100
5 Parallel Multiplication 103
5.1 Wallace Trees 103
5.2 Unsigned Array Multiplier 105
5.3 Two’s Complement Array Multiplier 108
5.3.1 Baugh- Wooley Two s Complement Multiplier 111
5.3.2 Pezaris Two’s Complement Multipliers 117
5.4 Modular Structure of Large Multiplier 120
5.4.1 Modular Structure 120
5.4.2 Additive Multiply Modules 123
5.4.3 Programmable Multiply Modules 125
References 130
Problems 132
6 Sequential Division 135
6.1 Subtract-and-Shifl Approach 135
6.2 Binary Restoring Division 138
6.3 Binary Non-Restoring Division 141
6.4 High-Radix Division 144
6.4.1 High-Radix Non-Restoring Division 144
6.4.2 SRT Division 146
6.4.3 Modified SRT Division 147
6.4.4 Robertson’s High-Radix Division 147
6.5 Convergence Division 150
6.5.1 Convergence Division Methodologies 152
6.5.2 Divider Implementing Convergence Division
Algorithm 155
6.6 Division by Divisor Reciprocation 157
References 162
Problems 164
7 Fast Array Dividers 167
7.1 Restoring Cellular Array Divider 167
7.2 Non-Restoring Cellular Array Divider 171