Area Array Packaging Handbook: Manufacturing and Assembly

494 Pages·2001·20.43 MB·English

by  Ken Gilleo

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AREA ARRAY
PACKAGING
HANDBOOK
Ken Gilleo
McGraw-Hill
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FM_Gilleo_137493-0 10/5/01 4:42 PM Page iv
Library of Congress Cataloging-in-Publication Data
Gilleo,Ken.
Area array packaging handbook :manufacturing and assembly / Ken Gilleo.
p. cm.
ISBN 0-07-137493-0
1. Ball grid array technology. 2. Microelectronic packaging. I. Title.
TK7870.15 .G54 2001
621.381’046—dc21 2001041051
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McGraw-Hill Packaging and Electronics Books
Coombs • PRINTEDCIRCUITSHANDBOOK5/e
Coombs • ELECTRONICINSTRUMENTHANDBOOK3/e
Harman • WIREBONDING
Harper • ELECTRONICSPACKAGINGANDINTERCONNECTIONHANDBOOK3/e
Harper • HIGHPERFORMANCEPRINTEDCIRCUITBOARDS
Hwang • MODERNSOLDERTECHNOLOGY
Jawitz • PRINTEDCIRCUITBOARDMATERIALSHANDBOOK
Lau • LOW-COSTFLIPCHIPTECHNOLOGIES
Lau • CHIPSCALEPACKAGE
Lau • ELECTRONICPACKAGING
Lau • BALLGRIDARRAYTECHNOLOGIES
Lau & Lee • MICROVIAS
Manko • SOLDERSANDSOLDERING4/e
Marks • PRINTEDCIRCUITASSEMBLYDESIGN
Martin • ELECTRONICFAILUREANALYSISHANDBOOK
Smith • THINFILMDEPOSITION
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Van Zant • MICROCHIPFABRICATION4/e
FM_Gilleo_137493-0 10/5/01 4:42 PM Page xxiii
Foreword
Jan Vardaman
TechSearch International
INTRODUCTION
Just as the semiconductor industry has seen a dramatic shift from through-hole to
surface-mount packages,another major change is underway—the shift from leads
to balls and from wires to bumps.
Ball grid array (BGA) packages are increasingly found in products including
personal computers, portable communications devices, workstations/servers, mid-
range and high-end computers,network and telecommunications systems,and even
automotive applications.
With the demand for smaller, lighter, thinner portable products has come the
need for semiconductor packaging and assembly technology to enable the produc-
tion of the new era of consumer products. Out of this need,the chip scale package
(CSP) was born.
Flip chip’s advantage over wire bond interconnection includes higher density
mounting, improved electrical performance, and improved reliability, as well as
improved manufacturability through gang bonding and the self-aligning nature of
solder bumps.
Demands from the consumer segment will continue to drive packaging develop-
ments—especially for small form factor packages. Mobile phones, in particular,
demand smaller,thinner,lighter packages. Many companies have adopted stacked
packages and flip chip is one of the interconnect options for the near future. The rate
of adoption and expanded use of ball grid arrays (BGAs), chip scale packages
(CSPs),and flip chip interconnect continues to amaze even the skeptics.
BGAS
The industry has made dramatic progress from the early days of the first BGA intro-
ductions. The first plastic ball grid array (PBGA) packages were in Motorola’s
pagers and radios,soon followed by products from Compaq Computer. These pack-
ages typically had less than 200 balls.
In 2001 more than 1.6 billion BGA packages of all types with pin counts over
2000 will ship. Ceramic ball grid array (CBGA) and ceramic column grid array
(CCGA) packages remain common for exceptionally high pin count ASICs and
processors. Shipping in high volume are 1,657-ball CCGAs for workstation/servers
and network system products. These packages have a 42.5 (cid:3) 42.5 mm body
size and a 1.0 mm column grid array pitch. Soon to be introduced are CCGAs with
more than 2000 solder columns.
xxiii
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xxiv FOREWORD
Tape ball grid array (TBGA) packages—mainly with wire bond interconnects—
continue to ship for many computer,telecommunications,and network systems.
The largest volume shipments are the plastic BGA (PBGA) packages,and per-
sonal computers remain the largest volume application. Intel has long moved its chip
set designs from plastic quad flat packages (PQFPs) to PBGAs—many pin counts
are in excess of 500 I/Os. Motorola has introduced some members of its PowerPC
family in PBGAs. While some of Intel’s CPUs are still shipping in its organic land
grid array (OLGA) package with solder balls, the majority of new Pentium ship-
ments are supplied in plastic pin grid arrays (PPGAs) as a result of demand for sock-
etable processors.
Perhaps the PC’s greatest future rival is the game machine, and BGAs are no
exception for the high pin count devices in these systems. Sony’s popular
PlayStation 2 contains an Emotion Engine processor packaged in a 540-ball PBGA
with a 42.5 (cid:3)42.5 mm body size and a 1.27 mm solder ball pitch. The graphic chip
is also packaged in a PBGA.
A variety of PBGA pin counts can be found in workstation/servers,telecommu-
nications,and network system products. High pin count designs from ASIC makers
continue to ship in BGAs. Sun Microsystems has some of the highest pin count
PBGA packages,one of which has 1848 balls with flip chip inside.
CSPs
Since the package first surfaced more than five years ago,CSPs have undergone the
most remarkable proliferation of any recently introduced package type. Today there
are more than 100 varieties of CSPs in existence with various configurations in
shipping numerous applications.
CSPs offer many of the advantages of bare die—tested die,size,weight,and low
profile,but at the same time provide a packaged solution. Low pin count devices are
increasingly being packaged in CSPs with larger volumes shipping every year.
Flex-based CSPs shipping in volume include Fujitsu’s FBGA,NEC’s D2BGA,
Sharp’s F.BGA, Tessera’s (cid:2)BGA, and Texas Instruments MicroStar™ bump chip
carrier (BCC)—Tessera’s patented (cid:2)BGA continues to be used for flash,although
laminate substrate alternatives have increased in popularity due to cost advantages
and the ability to handle die shrinks. Rigid substrate CSPs include Matsushita’s
ceramic-based packages and Motorola’s molded array package—adopted by almost
every contract assembly operation. High-volume lead frame CSPs include Fujitsu’s
bump chip carrier (BCC), Fujitsu’s SON, Matsushita’s QFN, and Amkor’s Micro
leadframe (MLF) package. These packages do not have solder balls and are targeted
for low I/O ((cid:4)85),inexpensive devices.
Stacked packages—typically with one flash memory and one SRAM—have
increased in volume dramatically in the last year. These packages use either type of
laminate substrates. Shipments of CSPs with more than two stacked devices,as well
as stacked CSP packages,will soon move into volume production.
One of the first products to make use of the small CSP was the camcorder. In
Sony’s first application,20 of the 40 ICs were CSPs. Sony’s DCR-PC7,introduced
in the fall of 1996,was one of the first products that made use of CSPs. With a body
size of just 59 (cid:3)129 (cid:3)118 mm,the camcorder contained 40 ICs—20 of them pack-
aged in CSPs and all with 0.5 mm pitch. Three Micro Star™ BGAs from Texas
Instruments (TI) Japan used TAB tape as the substrate and wire bonding as the chip-
to-substrate interconnect. One of NEC’s D2BGA packages used TAB tape as the sub-
strate,with a bumpless TAB inner lead bonding process used to interconnect the chip
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FOREWORD xxv
to the substrate. The remainder of the small area array packages,developed by Sony,
consisted of a laminate substrate and flip chip as the interconnect method.
Numerous companies followed Sony’s introduction—including JVC and
Matsushita—with numerous product introductions. These packages include flex-
based and rigid substrate packages—all with less than 1.0 mm pitch. Third- and
fourth-generation digital cameras and camcorders will continue to ship with
CSPs—making extreme miniaturization possible.
The unprecedented growth in demand for CSPs is being driven by the mobile
phone sector. Mobile phone production is now projected to increase beyond the
wildest expectations of many manufacturers—in some cases outpacing the supply
of key silicon devices such as flash memory. CSPs remain the packaging choice for
mobile phones for form factors reasons. This small package with I/Os of less than
1.0 mm,used in combination with microvia substrate technology,has enabled man-
ufacturers to shrink mobile phone size and weight—the smallest phone in Japan
weights about 58 g. While several companies have considered flip chip mounting to
achieve the same goals,CSPs continue to be the top packaging choice.
FLIP CHIP
Flip chip use can be categorized as either flip chip on board (FCOB) or flip chip in
package (FCIP). FCOB, or a flip chip device mounted directly on a motherboard,
includes such applications as automotive electronics,disk drives,driver ICs for flat
panel displays,watches,pagers,cellular phones,and contactless cards or RF ID tags.
FCIP is the mounting of a flip chip in packages such as ceramic ball grid arrays
(CBGA),column grid arrays (CCGA),and land grid arrays (CLGA),and plastic ball
grid arrays (PBGA). Inside the package, flip chip is increasingly used as an inter-
connect method for both performance and form factor reasons. FCIP can be found in
high-end mainframes and supercomputers,workstations and servers,mid-range sys-
tems,personal computers,network systems,and a variety of consumer products.
Flip chip is increasingly the interconnect method of choice for high-performance
ASICs. More than half the BGAs used by Sun Microsystems this year will be flip
chip inside,and in five years 90 percent of Sun’s BGAs will be flip chip. Flip chip
is also finding its way into the interconnect realm previously dominated by wire
bond. The potential expansion of flip chip technology into the midrange pin counts
represents a shift in the adoption of the technology as well as a maturing of the
industry. A recent example is the introduction of LSI Logic’s flip chip package tar-
geted at applications with between 300 and 1150 leads that require higher electrical
and thermal performance than that offered by wire bonded packages.
Flip chip interconnect is found in high volume in the personal computer market.
For several years,microprocessor speeds have required the use of flip chip intercon-
nect to achieve the performance specifications designed into silicon. FCIPs include
products such as AMD’s processor family, Intel’s Pentium products, Motorola’s
PowerPCs,and the new Transmetta microprocessor. In the near future chip sets are
also expected to use flip chip as the interconnect method inside the package.
Flip chip will continue to be found in a variety of emerging products. Wireless
applications such as Bluetooth modules are already shipping with flip chip inter-
connect.
Another new development is the proliferation of bumps for small die (less than
2 (cid:3) 2 mm), sometimes considered wafer level packages. Both of these develop-
ments represent not only improvements in flip chip infrastructure but also cost
reductions in the technology.
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xxvi FOREWORD
WAFER LEVEL PACKAGES: THE FUTURE STARTS
TODAY
Wafer level packages (WLPs) are packaged and tested at the wafer level,before the
dicing operation. Some bumped die may be considered wafer level packages if they
are not mounted inside a package and are not underfilled on the product board. For
example, most microprocessors and ASICs that use flip chip interconnect inside
the package are not wafer level packages. Dallas Semiconductor ships many low
lead count auto ID chips and battery controllers as bumped die that do not require
underfill when mounted on the product boards. These devices are called wafer
level packages.
Devices packaged at the wafer level,with or without bumps,continue to grow.
A variety of wafer level packages are shipping in volume—EEPROMs, voltage
regulators,op-amp devices,sensors,flash memory,and integrated passives.
Demands from the consumer and portable communication segments will con-
tinue to drive packaging developments—especially in wafer level CSPs and flip
chip. While in the early stages today, wafer level CSPs represent the wave of
the future.
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CONTENTS
Foreword xxiii
Section 1 Packaging Concepts and Design
Chapter 1. Introduction to Electronic Packaging 1.3
1.0 DEFINITION OF THE PACKAGE / 1.3
1.1 INTRODUCTION AND REQUIREMENTS / 1.3
1.2 PACKAGING EVOLUTIONS AND REVOLUTIONS / 1.4
1.2.1 SMT / 1.4
1.2.2 Perimeter Paralysis / 1.4
1.2.3 Direct Connections / 1.5
1.3 USEFUL VERSUS ESSENTIAL FEATURES / 1.7
1.3.1 Geometric Translation / 1.7
1.3.2 Material Compatibility:IC to PWB / 1.7
1.3.3 Environmental and Mechanical Protection / 1.8
1.3.4 Handling Ease / 1.8
1.3.5 Standardization / 1.8
1.3.6 Facilitate Auto Assembly / 1.8
1.3.7 Removability/Reworkability / 1.9
1.3.8 Performance Enhancement / 1.9
1.3.9 Thermal Management / 1.9
1.4 EARLY PACKAGE DEVELOPMENT / 1.10
1.5 ELECTRICAL CONNECTIONS / 1.12
1.5.1 First Level:Chip to Carrier / 1.12
1.5.2 DCA (Flip Chip) / 1.12
1.5.3 Wire Bonded (WB) / 1.12
1.5.4 Tape Automated Bonding (TAB) / 1.12
1.5.5 Second Level:To PWB / 1.13
1.6 PACKAGING MATERIALS / 1.14
1.6.1 Metal / 1.14
1.6.2 Ceramic / 1.14
1.6.3 Plastic / 1.15
1.7 PACKAGE STYLES / 1.17
1.7.1 Lead Frame / 1.17
1.7.2 Chip Carriers/Platforms / 1.17
1.8 PROTECTION / 1.18
1.8.1 Hermetic / 1.18
1.8.2 Molding Compounds / 1.18
1.8.3 Liquid Encapsulants / 1.18
1.8.4 Underfill / 1.19
1.8.5 Chip Passivation Only / 1.19
1.9 PACKAGE ASSEMBLY / 1.19
1.9.1 Issues with Area Array / 1.19
1.9.2 Soldering / 1.19
1.9.3 Conductive Adhesives / 1.19
v
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vi CONTENTS
1.10 PACKAGE RELIABILITY / 1.20
1.11 FUTURE EXPECTATIONS / 1.20
Chapter 2. Electronics Industry Overview 2.1
2.0 THE ELECTRONICS INDUSTRY TODAY / 2.1
2.1 THE ANATOMY OF A SYSTEM / 2.1
2.2 THE ELECTRONICS INDUSTRY IN 2020 / 2.4
2.2.1 The Structure of the Electronics Industry in 2020 / 2.7
Chapter 3. Trends/Drivers in the Electronics Manufacturing Industry 3.1
3.0 INTRODUCTION / 3.1
3.1 PARALLEL AND DATA-DRIVEN ASSEMBLY PROCESSES / 3.3
3.1.1 Importance of Throughput / 3.3
3.1.2 Parallel and Data-Driven Processes / 3.4
3.1.3 Developments in Parallel and Data-Driven Processes / 3.5
3.2 SOFTWARE AND LINE INTEGRATION / 3.6
3.2.1 Software and Machine Vision Replace Steel / 3.6
3.2.2 Line Integration / 3.9
3.3 SLOW SECONDARY PROCESSES BECOME NICHE / 3.9
3.4 THROUGHPUT,YIELD,AND COST GUARANTEES:TOTAL SOLUTIONS / 3.10
3.5 THROUGH-HOLE ASSEMBLY REMAINS AND ODD-FORM ASSEMBLY EMERGES / 3.12
3.5.1 Through-Hole Assembly / 3.12
3.5.2 Through-Hole Equipment / 3.13
3.5.3 Nonstandard Automated Assembly / 3.14
3.5.4 Conclusion / 3.15
3.6 KNOWLEDGE / 3.15
3.6.1 Knowledge:A Most Valuable Asset / 3.16
3.7 PWB/FLEX LINE WIDTHS FROM 6 TO 3 MILS AS STANDARD,MICROVIAS,
AND BUM PWBs PROLIFERATE / 3.16
3.7.1 Multilayer versus Built-Up / 3.18
3.8 LEAD-FREE IMPACT / 3.20
3.9 PASSIVES:THE GROWTH CONTINUES / 3.21
3.9.1 Why Is Passive Use Growing? / 3.22
3.9.2 What Are the Trends in Passives? / 3.22
3.9.3 What Is the Future for Passives? / 3.23
3.10 NOTES AND REFERENCES / 3.25
Chapter 4. Area Array Packaging 4.1
4.0 INTRODUCTION / 4.1
4.1 BASIC ELEMENTS OF A PACKAGE / 4.1
4.1.1 Device / 4.1
4.1.2 Wiring or Routing / 4.2
4.1.3 Packaging Enclosure / 4.3
4.1.4 Board-Level Joining System / 4.3
4.2 OVERVIEW OF TYPES OF AREA ARRAY PACKAGES / 4.3
4.3 ADVANTAGES OF AREA ARRAY / 4.5
4.3.1 Density / 4.5
4.3.2 Thermal Management / 4.5
4.3.3 Multiple Chips / 4.6
4.3.4 Built-In Solder Source / 4.7
4.3.5 Self-Centering / 4.7
4.3.6 High Assembly Yield / 4.7
4.4 ISSUES WITH AREA ARRAY / 4.8
4.4.1 Inspection / 4.8
4.4.2 Voids / 4.8
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CONTENTS vii
4.4.3 Cost / 4.8
4.4.4 Planarity / 4.9
4.4.5 Moisture Absorption / 4.9
4.4.6 Rework / 4.10
4.5 FIRST-LEVEL INTERCONNECT (CHIP TO CARRIER) / 4.10
4.5.1 Wire Bonding / 4.10
4.5.2 TAB (Tape Automated Bonding) / 4.10
4.5.3 Flip Chip (FC) / 4.10
4.6 PROTECTION METHODS / 4.11
4.6.1 Epoxy Transfer Molding / 4.11
4.6.2 Liquid Encapsulation / 4.11
4.6.3 Lid Seal / 4.11
4.6.4 None? / 4.11
4.7 SECOND-LEVEL INTERCONNECT (PACKAGE TO PWB) / 4.12
4.7.1 Pins:Pin Grid Array (PGA) / 4.12
4.7.2 Eutectic Solder Spheres / 4.12
4.7.3 Nonfusing Metal Spheres,Bumps,or Columns / 4.12
4.7.4 Conductive Adhesives / 4.12
4.8 THE PLASTIC BALL GRID ARRAY (PBGA) / 4.13
4.8.1 Die-Up / 4.13
4.8.2 Die-Down / 4.13
4.9 METAL PACKAGES / 4.13
4.9.1 Hermetic / 4.13
4.9.2 Encapsulated / 4.14
4.10 CERAMIC / 4.14
4.11 CSP PRODUCTS / 4.14
4.12 FLIP CHIP:IS IT A TRUE PACKAGE? / 4.14
4.13 RELIABILITY / 4.14
4.14 FUTURE EXPECTATIONS / 4.14
Chapter 5. Stacked/3D Packages 5.1
5.0 INTRODUCTION / 5.1
5.1 THE FOURTH WAVE OF PACKAGING INNOVATION / 5.1
5.2 REVIEW OF CHIP-SCALE PACKAGING (CSP) AND STACKED CSP (S-CSP) ADVANCES / 5.4
5.3 HANDSET FUNCTIONAL SYSTEM INTEGRATION / 5.4
5.4 CSP TO S-CSP ADOPTION IN HANDSETS / 5.6
5.5 S-CSP GROWTH:STANDARDS AND INFRASTRUCTURE / 5.7
5.6 THREE-CHIP INTEGRATION IN S-CSP PLATFORMS / 5.12
5.7 FLIP CHIP (FC) AND S-CSP TECHNOLOGY ROADMAPS / 5.14
5.8 FLIP CHIP (FC) AND WIRE-BOND STACK-DIE INTEGRATION / 5.15
5.9 CONCLUSION / 5.16
5.10 REFERENCES / 5.19
Chapter 6. Compliant IC Packaging 6.1
6.0 INTRODUCTION / 6.1
6.1 PACKAGE TECHNOLOGY OBJECTIVES / 6.2
6.2 I/O PLACEMENT / 6.2
6.3 COMPLIANT CSP CONSTRUCTION / 6.2
6.3.1 Materials of Construction / 6.3
6.3.2 Bond Lead Design / 6.5
6.3.3 Principles of Operation / 6.5
6.3.4 Other Compliant (cid:2)BGA Configurations / 6.5
6.3.5 I/O Configurations / 6.6
6.3.6 Multiple Metal Layers / 6.8
6.3.7 Adapting to Die Shrink / 6.8
6.4 MANUFACTURING PROCESSES / 6.9
6.4.1 Original Process / 6.9