Application Specific Instruction-set Processor Using a Parametrizable multi-SIMD Synthesizeable ...

60 Pages·2016·1.6 MB·English

MASTER’S THESIS | LUND UNIVERSITY 2016
Application Specific Instruction-set Processor Using
a Parametrizable multi-SIMD Synthesizeable Model
Supporting Design Space Exploration
Magnus Hultin
Department of Computer Science
Faculty of Engineering LTH
ISSN 1650-2884
LU-CS-EX 2016-14

Application Specific Instruction-set
Processor Using a Parametrizable
multi-SIMD Synthesizeable Model
Supporting Design Space Exploration
Magnus Hultin
[email protected]
May 18, 2016
Master’s thesis work carried out at
the Department of Computer Science, Lund University.
Supervisor: FlaviusGruian,[email protected]
Examiner: KrzysztofKuchcinski,[email protected]

Abstract
In this thesis, we provide a synthesizable model for supporting design
spaceexplorationofapplication-specificinstruction-setprocessors. Themodel
is written in a high-level of abstraction hardware description language Blue-
spec System Verilog and is parametrized to support different configurations
for use in the design space exploration. To test the model, different applica-
tionsfromthemediadomainwasselectedtorunonsomeoftheconfigurations
from the design space exploration. The applications were also run on a stan-
dardgeneralprocessorforcomparison.
The results show that there is a performance gain compared to the stan-
dardprocessor,butwithahighercostofresources. Withtheutilizationofthe
resources the scheduling of the applications turned out to be critical for this
performance gain. The synthesizable model also shows that there is a con-
sideration of the maximum clock frequency and memory constraints that the
theoreticaldesignspaceexplorationmodeldoesnottakeintoaccount.
Keywords: MSc,VLIW,SIMD,processor,Bluespec,DSE
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Acknowledgements
First, I would like to thank my supervisor Flavius Gruian for his valuable feedback and
support throughout the project. This project would not be possible without his help and
patience.
IwouldliketothankMehmetAliArslanforhishelpanddiscussions.
IwouldliketothankmyexaminerKrzysztofKuchcinskiforhisfeedbackonthethesis.
IwouldliketothankLarsNilssonandAndersBrucefortheircomputersupport.
Finally I would like to thank my family for their support and my sambo, Yuqiao Xie for
herloveandsupport.
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Contents
1 Introduction 7
1.1 ProblemDefinition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 RelatedWork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Background 11
2.1 DesignSpaceExploration . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 RISCPipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 VLIW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4 SIMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5 SchedulingTechniques . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.1 SingleIteration . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.2 OverlappedExecution . . . . . . . . . . . . . . . . . . . . . . . 16
2.5.3 LoopVectorization . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.5.4 LoopVectorizedthenOverlappedExecution . . . . . . . . . . . 18
2.6 BluespecSystemVerilog . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 Implementation 21
3.1 EarlyVersions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2 FinalVersion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3 ThePipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.1 InstructionFetch . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.2 RegisterFetchStage . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.3 PermutationStage . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.4 ExecuteStage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.5 Write-backStage . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4 RegisterFileModule . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5 Parameterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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CONTENTS
4 Evaluation 31
4.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2 ExperimentalResults . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5 Discussion 37
5.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.2 ResourceUsage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3 ScheduleTechniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.4 BluespecSystemVerilog . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.5 DesignSpaceExploration . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.6 FutureWorkandImprovements . . . . . . . . . . . . . . . . . . . . . . 40
6 Conclusion 41
Bibliography 43
AppendixA MatrixMultiplierApplicationinC 47
AppendixB DFGforapartofFDCT 49
AppendixC BluespecFIFOinterface 51
AppendixD FiniteStateMachineExample 53
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