Application-Specific Hardware Architecture Design with VHDL

191 Pages·2018·4.48 MB·English

by  Bogdan Belean (auth.)

Signals and Communication Technology
Bogdan Belean
Application-
Specific Hardware
Architecture
Design with VHDL
Signals and Communication Technology
More information about this series at http://www.springer.com/series/4748
Bogdan Belean
fi
Application-Speci c
Hardware Architecture
Design with VHDL
123
Bogdan Belean
National Institute for Research
andDevelopmentof Isotopic
andMolecular Technologies
Cluj-Napoca
Romania
ISSN 1860-4862 ISSN 1860-4870 (electronic)
Signals andCommunication Technology
ISBN978-3-319-65023-4 ISBN978-3-319-65025-8 (eBook)
https://doi.org/10.1007/978-3-319-65025-8
LibraryofCongressControlNumber:2017949155
©SpringerInternationalPublishingAG2018
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To my wife Ramona and to my sons Vlad and
Mihnea
Contents
1 Introduction to Digital Design with VHDL.... .... .... ..... .... 1
1.1 Digital Systems—Introductory Notes .. .... .... .... ..... .... 1
1.2 Levels of Abstraction. ..... .... .... .... .... .... ..... .... 3
1.3 The VHDL Hardware Description Language .... .... ..... .... 6
1.3.1 Overview of Hardware Description Languages. ..... .... 6
1.3.2 VHDL Code Structure ... .... .... .... .... ..... .... 8
1.3.3 Data Types and Operators. .... .... .... .... ..... .... 10
1.4 Combinational Logic, Sequential Logic and VHDL... ..... .... 14
1.4.1 Concurrent VHDL Code.. .... .... .... .... ..... .... 15
1.4.2 Sequential VHDL Code .. .... .... .... .... ..... .... 19
1.5 Structural Description with VHDL.... .... .... .... ..... .... 25
1.6 VHDL Code for Simulation Test-Benches .. .... .... ..... .... 32
1.7 Finite State Machines. ..... .... .... .... .... .... ..... .... 40
1.8 Methodology for Digital Design with VHDL.... .... ..... .... 47
1.9 Conclusions .... .... ..... .... .... .... .... .... ..... .... 48
Appendix A .... .... .... ..... .... .... .... .... .... ..... .... 49
Appendix B. .... .... .... ..... .... .... .... .... .... ..... .... 50
Appendix C. .... .... .... ..... .... .... .... .... .... ..... .... 53
References.. .... .... .... ..... .... .... .... .... .... ..... .... 54
2 Hardware Architectures for Channel Encoding in Information
Transmission Systems.... ..... .... .... .... .... .... ..... .... 55
2.1 Introduction to Information Transmission System. .... ..... .... 55
2.1.1 Modelling an Information Transmission System..... .... 56
2.2 Introduction to Channel Encoding for Error Control... ..... .... 58
2.2.1 Representation of Error Control Codes... .... ..... .... 58
2.2.2 Classification of Error Control Codes.... .... ..... .... 59
2.2.3 Error Control Codes Parameters .... .... .... ..... .... 60
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2.3 Block Codes.... .... ..... .... .... .... .... .... ..... .... 61
2.3.1 Coding Equations ... .... .... .... .... .... ..... .... 61
2.3.2 Decoding Equations . .... .... .... .... .... ..... .... 63
2.4 Hamming Coder/Decoder Implementations.. .... .... ..... .... 64
2.4.1 Encoder Implementation .. .... .... .... .... ..... .... 65
2.5 Cyclic Codes Principles .... .... .... .... .... .... ..... .... 71
2.6 Cyclic Codes Encoder and Decoder Implementations.. ..... .... 72
2.6.1 Cyclic Decoder Architectures .. .... .... .... ..... .... 77
2.7 Conclusions .... .... ..... .... .... .... .... .... ..... .... 77
References.. .... .... .... ..... .... .... .... .... .... ..... .... 78
3 High-Throughput Hardware Architecture for LDPC Decoders. .... 79
3.1 Introduction to LDPC Codes for Digital Communication.... .... 80
3.2 Decoding Algorithms Description. .... .... .... .... ..... .... 82
3.3 Low-Complexity Approach for LDPC Decoding Process.... .... 83
3.4 Conclusions .... .... ..... .... .... .... .... .... ..... .... 96
References.. .... .... .... ..... .... .... .... .... .... ..... .... 96
4 Hardware Architecture for Edge Detection.... .... .... ..... .... 99
4.1 Introduction—Microarray Image Processing System... ..... .... 99
4.2 Hardware Architecture for Image Convolution... .... ..... .... 102
4.2.1 Convolution in Digital Image Processing . .... ..... .... 102
4.2.2 Hardware Implementation for Convolution.... ..... .... 104
4.3 Hardware Architecture for the Canny Filter . .... .... ..... .... 110
4.3.1 Canny Edge Detection ... .... .... .... .... ..... .... 110
4.3.2 Hardware Implementation of the Canny Edge
Detector . .... ..... .... .... .... .... .... ..... .... 113
4.3.3 Timing Considerations for the Canny Edge
Detection Architecture.... .... .... .... .... ..... .... 116
4.3.4 System-on-a-Chip (SoC) for Edge Detection... ..... .... 120
4.4 Canny Architecture Applied in Microarray Image
Processing.. .... .... ..... .... .... .... .... .... ..... .... 126
Appendix D .... .... .... ..... .... .... .... .... .... ..... .... 128
References.. .... .... .... ..... .... .... .... .... .... ..... .... 140
5 Hardware Architectures for Iterative Algorithms
Implementations .... .... ..... .... .... .... .... .... ..... .... 141
5.1 Hardware Architecture for Shock Filters Applied
in Microarray Image Processing.. .... .... .... .... ..... .... 141
5.1.1 Partially Differential Equations in Image Processing.. .... 141
5.1.2 Shock Filters.. ..... .... .... .... .... .... ..... .... 142
5.1.3 Shock Filter Application—Microarray Grid
Alignment.... ..... .... .... .... .... .... ..... .... 144
5.1.4 Hardware Architecture for Shock Filters.. .... ..... .... 149
5.1.5 Timing Considerations ... .... .... .... .... ..... .... 151
Contents ix
5.2 Hardware Architecture for Anisotropic Diffusion Applied
in Satellite Imagery... ..... .... .... .... .... .... ..... .... 152
5.2.1 Introduction to Satellite Imagery.... .... .... ..... .... 152
5.2.2 Perona and Malik Filter Formulation. .... .... ..... .... 153
5.2.3 Hardware Implementation for Parallel Computation
of Anisotropic Diffusion.. .... .... .... .... ..... .... 156
5.2.4 Application-Specific Hardware Architecture for Perona
and Malik Filter in Satellite Imagery—Case Study... .... 158
5.3 Conclusions .... .... ..... .... .... .... .... .... ..... .... 160
References.. .... .... .... ..... .... .... .... .... .... ..... .... 161
6 EfficientHoughTransformImplementationUsingCAMMemories
Applied on Satellite Imagery ... .... .... .... .... .... ..... .... 163
6.1 Satellite Imagery for Oil Slick Detection ... .... .... ..... .... 164
6.1.1 Circular Hough Transform .... .... .... .... ..... .... 164
6.1.2 CAM-Based Approach for Efficient Hough Transform
Implementation..... .... .... .... .... .... ..... .... 165
6.2 Memory Implementation Using FPGA. .... .... .... ..... .... 167
6.2.1 Memory Types ..... .... .... .... .... .... ..... .... 168
6.2.2 Inferred and Instantiated Memories Using VHDL.... .... 168
6.2.3 Memory Organization.... .... .... .... .... ..... .... 174
6.3 CAM Memory Implementation Using VHDL.... .... ..... .... 177
6.4 Conclusions .... .... ..... .... .... .... .... .... ..... .... 181
References.. .... .... .... ..... .... .... .... .... .... ..... .... 181
About the Author
Bogdan Belean was born in Tirgu-Mures, Romania, on February 7, 1983. He
received the B.E. and Ph.D. degrees in Electronics and Telecommunication
Engineering from the Technical University of Cluj-Napoca, Romania,in 2006 and
2010, respectively. Since 2008, he is involved in didactic activates as a research
assistant and later as a Lecturer within the Technical University of Cluj-Napoca,
Department of Communications. In 2011, Dr. Belean joined the Department of
Mass Spectrometry, Chromatography and Applied Physics within the National
Institute for Research and Development of Isotopic and Molecular Technology,
Cluj-Napoca. In 2014, he became a member of the Center for Research and
Advanced Technologies for Alternative Energies (CETATEA) within the same
national institute. His research interests include signal and image processing,
bioinformatics, application-specific hardware architectures for parallel computing
and advanced technologies for alternative energies. His research results include
over30publicationsandtwoopen-sourcesoftwaresolutionsforbiomedicalimage
analysis.
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